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165 Publications
1997 | Conference Paper | LibreCat-ID: 13009
STARBIST: Scan Autocorrelated Random Pattern Generation
K.-H. Tsai, S. Hellebrand, M. Marek-Sadowska, J. Rajski, in: 34th ACM/IEEE Design Automation Conference (DAC’97), IEEE, Anaheim, CA, USA, 1997.
LibreCat
| DOI
K.-H. Tsai, S. Hellebrand, M. Marek-Sadowska, J. Rajski, in: 34th ACM/IEEE Design Automation Conference (DAC’97), IEEE, Anaheim, CA, USA, 1997.
1996 | Misc | LibreCat-ID: 13087
Using Embedded Processors for BIST
S. Hellebrand, H.-J. Wunderlich, Using Embedded Processors for BIST, 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1996.
LibreCat
S. Hellebrand, H.-J. Wunderlich, Using Embedded Processors for BIST, 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1996.
1996 | Misc | LibreCat-ID: 13088
Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, Mixed-Mode BIST Using Embedded Processors, 2nd IEEE International On-Line Testing Workshop. Biarritz, France, 1996.
LibreCat
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, Mixed-Mode BIST Using Embedded Processors, 2nd IEEE International On-Line Testing Workshop. Biarritz, France, 1996.
1996 | Conference Paper | LibreCat-ID: 13010
Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, in: IEEE International Test Conference (ITC’96), IEEE, Washington, DC, USA, 1996, pp. 195–204.
LibreCat
| DOI
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, in: IEEE International Test Conference (ITC’96), IEEE, Washington, DC, USA, 1996, pp. 195–204.
1995 | Report | LibreCat-ID: 13026
Synthesis Procedures for Self-Testable Controllers
S. Hellebrand, H.-J. Wunderlich, Synthesis Procedures for Self-Testable Controllers, University of Siegen, Germany, 1995.
LibreCat
S. Hellebrand, H.-J. Wunderlich, Synthesis Procedures for Self-Testable Controllers, University of Siegen, Germany, 1995.
1995 | Report | LibreCat-ID: 13027
Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis
S. Hellebrand, H.-J. Wunderlich, F. Goncalves, J. Paulo Teixeira, Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis, University Siegen, Germany, 1995.
LibreCat
S. Hellebrand, H.-J. Wunderlich, F. Goncalves, J. Paulo Teixeira, Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis, University Siegen, Germany, 1995.
1995 | Report | LibreCat-ID: 13028
Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing
S. Hellebrand, M. Herzog, H.-J. Wunderlich, Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing, University of Siegen, Germany, 1995.
LibreCat
S. Hellebrand, M. Herzog, H.-J. Wunderlich, Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing, University of Siegen, Germany, 1995.
1995 | Misc | LibreCat-ID: 13086
Pattern Generation for a Deterministic BIST Scheme
S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich, Pattern Generation for a Deterministic BIST Scheme, 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1995.
LibreCat
S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich, Pattern Generation for a Deterministic BIST Scheme, 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1995.
1995 | Journal Article | LibreCat-ID: 13011
Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois, IEEE Transactions on Computers 44 (1995) 223–233.
LibreCat
| DOI
S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois, IEEE Transactions on Computers 44 (1995) 223–233.
1995 | Conference Paper | LibreCat-ID: 13012
Pattern Generation for a Deterministic BIST Scheme
S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich, in: ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), IEEE, San Jose, CA, USA, 1995, pp. 88–94.
LibreCat
| DOI
S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich, in: ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), IEEE, San Jose, CA, USA, 1995, pp. 88–94.