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122 Publications


2014 | Conference Paper | LibreCat-ID: 377
Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In Proceedings of Field-Programmable Custom Computing Machines (FCCM) (pp. 222–229). IEEE. https://doi.org/10.1109/FCCM.2014.67
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2014 | Journal Article | LibreCat-ID: 365
Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2014). Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 7(2). https://doi.org/10.1145/2617596
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2014 | Journal Article | LibreCat-ID: 328
Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., & Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro, 34(1), 60–71. https://doi.org/10.1109/MM.2013.110
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2014 | Book Chapter | LibreCat-ID: 335
Platzner, M., & Plessl, C. (2014). Verschiebungen an der Grenze zwischen Hardware und Software. In J. Künsemöller, N. O. Eke, L. Foit, & T. Kaerlein (Eds.), Logiken strukturbildender Prozesse: Automatismen (pp. 123–144). Paderborn: Wilhelm Fink.
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2014 | Conference Paper | LibreCat-ID: 406
Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) (pp. 1–8). IEEE. https://doi.org/10.1109/ReConFig.2014.7032535
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2014 | Conference Paper | LibreCat-ID: 1778
C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., … Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA) (pp. 142–149). IEEE. https://doi.org/10.1109/ISPA.2014.27
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2014 | Conference Paper | LibreCat-ID: 1780
C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino, M., … Bolchini, C. (2014). SAVE: Towards efficient resource management in heterogeneous system architectures. In Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer. https://doi.org/10.1007/978-3-319-05960-0_38
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2014 | Journal Article | LibreCat-ID: 363
Agne, A., Hangmann, H., Happe, M., Platzner, M., & Plessl, C. (2014). Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems, 38(8, Part B), 911–919. https://doi.org/10.1016/j.micpro.2013.12.001
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2013 | Conference Paper | LibreCat-ID: 528
Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In Proceedings of the International Conference on Field-Programmable Technology (FPT) (pp. 386–389). IEEE. https://doi.org/10.1109/FPT.2013.6718394
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2013 | Conference Paper | LibreCat-ID: 505
Happe, M., Kling, P., Plessl, C., Platzner, M., & Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS). IEEE. https://doi.org/10.1109/ISORC.2013.6913232
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2013 | Conference Paper | LibreCat-ID: 1787
Suess, T., Schoenrock, A., Meisner, S., & Plessl, C. (2013). Parallel Macro Pipelining on the Intel SCC Many-Core Computer. In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW) (pp. 64–73). Washington, DC, USA: IEEE Computer Society. https://doi.org/10.1109/IPDPSW.2013.136
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2013 | Mastersthesis | LibreCat-ID: 521
Riebler, H. (2013). Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs. Universität Paderborn.
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2012 | Conference Paper | LibreCat-ID: 2107
Grunzke, R., Birkenheuer, G., Blunk, D., Breuers, S., Brinkmann, A., Gesing, S., … Zink, A. (2012). A Data Driven Science Gateway for Computational Workflows. In Proc. UNICORE Summit.
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2012 | Conference Paper | LibreCat-ID: 612
Rüthing, C., Happe, M., Agne, A., & Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) (pp. 559–562). IEEE. https://doi.org/10.1109/FPL.2012.6339370
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2012 | Journal Article | LibreCat-ID: 2108
Schumacher, T., Plessl, C., & Platzner, M. (2012). IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems, 36(2), 110–126. https://doi.org/10.1016/j.micpro.2011.04.002
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2012 | Journal Article | LibreCat-ID: 2177
Grad, M., & Plessl, C. (2012). On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. Int. Journal of Reconfigurable Computing (IJRC). https://doi.org/10.1155/2012/418315
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2012 | Conference Paper | LibreCat-ID: 567
Barrio, P., Carreras, C., Sierra, R., Kenter, T., & Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In Proceedings of the International Conference on High Performance Computing and Simulation (HPCS) (pp. 559–565). IEEE. https://doi.org/10.1109/HPCSim.2012.6266973
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2012 | Conference Paper | LibreCat-ID: 2180
Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2012). Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS).
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2012 | Misc | LibreCat-ID: 587
Plessl, C., Platzner, M., Agne, A., Happe, M., & Lübbers, E. (2012). Programming models for reconfigurable heterogeneous multi-cores. Awareness Magazine.
LibreCat | Files available
 

2012 | Conference Paper | LibreCat-ID: 615
Happe, M., Hangmann, H., Agne, A., & Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig) (pp. 1–8). IEEE. https://doi.org/10.1109/ReConFig.2012.6416745
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2012 | Conference Paper | LibreCat-ID: 2106
Meyer, B., Schumacher, J., Plessl, C., & Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (pp. 189–196). IEEE. https://doi.org/10.1109/FPL.2012.6339370
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2012 | Conference Paper | LibreCat-ID: 609
Happe, M., Agne, A., Plessl, C., & Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. In Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) (pp. 8–9).
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2012 | Conference Paper | LibreCat-ID: 591
Kenter, T., Plessl, C., & Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) (pp. 1–8). IEEE. https://doi.org/10.1109/ReConFig.2012.6416773
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2011 | Conference Paper | LibreCat-ID: 2191
Kenter, T., Plessl, C., Platzner, M., & Kauschke, M. (2011). Estimation and Partitioning for CPU-Accelerator Architectures. In Intel European Research and Innovation Conference.
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2011 | Conference Paper | LibreCat-ID: 656
Happe, M., Agne, A., & Plessl, C. (2011). Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. In Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig) (pp. 55–60). IEEE. https://doi.org/10.1109/ReConFig.2011.59
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2011 | Book Chapter | LibreCat-ID: 10737
Sekanina, L., Walker, J. A., Kaufmann, P., Plessl, C., & Platzner, M. (2011). Evolution of Electronic Circuits. In Cartesian Genetic Programming (pp. 125–179). Springer Berlin Heidelberg.
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2011 | Conference Paper | LibreCat-ID: 2200
Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2011). Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. In Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA) (pp. 177–180). New York, NY, USA: ACM. https://doi.org/10.1145/1950413.1950448
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2011 | Conference Paper | LibreCat-ID: 2193
Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2011). Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) (pp. 223–226). IEEE Computer Society. https://doi.org/10.1109/ASAP.2011.6043273
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2011 | Conference Paper | LibreCat-ID: 2198
Grad, M., & Plessl, C. (2011). Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. In Proc. Reconfigurable Architectures Workshop (RAW) (pp. 278–285). IEEE Computer Society. https://doi.org/10.1109/IPDPS.2011.153
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2011 | Journal Article | LibreCat-ID: 2201
Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2011). FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. Int. Journal of Recon- Figurable Computing (IJRC). https://doi.org/10.1155/2011/760954
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2011 | Conference Paper | LibreCat-ID: 2194
Meyer, B., Plessl, C., & Förstner, J. (2011). Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. In Symp. on Application Accelerators in High Performance Computing (SAAHPC) (pp. 60–63). IEEE Computer Society. https://doi.org/10.1109/SAAHPC.2011.12
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2011 | Book Chapter | LibreCat-ID: 2202
Plessl, C., & Platzner, M. (2011). Hardware Virtualization on Dynamically Reconfigurable Embedded Processors. In M. Khalgui & H.-M. Hanisch (Eds.), Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility. Hershey, PA, USA: IGI Global. https://doi.org/10.4018/978-1-60960-086-0
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2010 | Conference (Editor) | LibreCat-ID: 2222
Plaks, T. P., Andrews, D., DeMara, R., Lam, H., Lee, J., Plessl, C., & Stitt, G. (Eds.). (2010). Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press.
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2010 | Conference Paper | LibreCat-ID: 2227
Woehrle, M., Plessl, C., & Thiele, L. (2010). Rupeas: Ruby Powered Event Analysis DSL. In Proc. Int. Conf. Networked Sensing Systems (INSS) (pp. 245–248). IEEE. https://doi.org/10.1109/INSS.2010.5572211
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2010 | Conference Paper | LibreCat-ID: 2216
Grad, M., & Plessl, C. (2010). Pruning the Design Space for Just-In-Time Processor Customization. In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) (pp. 67–72). Los Alamitos, CA, USA: IEEE Computer Society. https://doi.org/10.1109/ReConFig.2010.19
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2010 | Conference Paper | LibreCat-ID: 2223
Lübbers, E., Platzner, M., Plessl, C., Keller, A., & Plattner, B. (2010). Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 225–231). CSREA Press.
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2010 | Conference Paper | LibreCat-ID: 2228
Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2010). Performance Estimation for the Exploration of CPU-Accelerator Architectures. In O. Hammami & S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA).
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2010 | Conference Paper | LibreCat-ID: 2224
Grad, M., & Plessl, C. (2010). An Open Source Circuit Library with Benchmarking Facilities. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 144–150). CSREA Press.
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2010 | Conference Paper | LibreCat-ID: 2206
Keller, A., Plattner, B., Lübbers, E., Platzner, M., & Plessl, C. (2010). Reconfigurable Nodes for Future Networks. In Proc. IEEE Globecom Workshop on Network of the Future (FutureNet) (pp. 372–376). IEEE. https://doi.org/10.1109/GLOCOMW.2010.5700341
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2010 | Conference Paper | LibreCat-ID: 2220
Andrews, D., & Plessl, C. (2010). Configurable Processor Architectures: History and Trends. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (p. 165). CSREA Press.
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2010 | Conference Paper | LibreCat-ID: 2226
Beisel, T., Niekamp, M., & Plessl, C. (2010). Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators. In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) (pp. 65–72). IEEE Computer Society. https://doi.org/10.1109/ASAP.2010.5540798
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2009 | Conference Paper | LibreCat-ID: 2350
Schumacher, T., Plessl, C., & Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) (pp. 275–278). IEEE Computer Society. https://doi.org/10.1109/FCCM.2009.25
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2009 | Conference Paper | LibreCat-ID: 2261
Schumacher, T., Plessl, C., & Platzner, M. (2009). An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) (pp. 338–344). IEEE.
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2009 | Conference Paper | LibreCat-ID: 2262
Kaufmann, P., Plessl, C., & Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. In Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS) (pp. 11–18). Los Alamitos, CA, USA: IEEE Computer Society.
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2009 | Conference Paper | LibreCat-ID: 2263
Grad, M., & Plessl, C. (2009). Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 319–322). USA: CSREA Press.
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2009 | Conference Paper | LibreCat-ID: 2352
Beutel, J., Gruber, S., Hasler, A., Lim, R., Meier, A., Plessl, C., … Yuecel, M. (2009). PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. In Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN) (pp. 265–276). Washington, DC, USA: IEEE Computer Society.
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2009 | Report | LibreCat-ID: 2353
Woehrle, M., Plessl, C., & Thiele, L. (2009). Rupeas: Ruby Powered Event Analysis DSL. Computer Engineering and Networks Lab, ETH Zurich.
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2009 | Conference Paper | LibreCat-ID: 2238
Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2009). Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) (pp. 119–124). Los Alamitos, CA, USA: IEEE Computer Society. https://doi.org/10.1109/ReConFig.2009.32
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2008 | Conference Paper | LibreCat-ID: 2370
Woehrle, M., Plessl, C., Lim, R., Beutel, J., & Thiele, L. (2008). EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks. In IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC) (pp. 201–208). Los Alamitos, CA, USA: IEEE Computer Society. https://doi.org/10.1109/SUTC.2008.24
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2008 | Conference Paper | LibreCat-ID: 2364
Schumacher, T., Meiche, R., Kaufmann, P., Lübbers, E., Plessl, C., & Platzner, M. (2008). A Hardware Accelerator for k-th Nearest Neighbor Thinning. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 245–251). CSREA Press.
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