Please note that LibreCat no longer supports Internet Explorer versions 8 or 9 (or earlier).
We recommend upgrading to the latest Internet Explorer, Google Chrome, or Firefox.
450 Publications
2001 | Journal Article | LibreCat-ID: 10713
Mencer, O., Platzner, M., Morf, M., & J. Flynn, M. (2001). Object-oriented domain specific compilers for programming FPGAs. {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems, 9(1), 205–210. https://doi.org/10.1109/92.920835
LibreCat
| DOI
2001 | Misc | LibreCat-ID: 13463
Enzler, R., & Platzner, M. (2001). Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1).
LibreCat
2000 | Journal Article | LibreCat-ID: 6507
Platzner, M. (2000). Reconfigurable accelerators for combinatorial problems. Computer, 33(4), 58–60. https://doi.org/10.1109/2.839322
LibreCat
| DOI
2000 | Journal Article | LibreCat-ID: 10606
Eisenring, M., & Platzner, M. (2000). Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems. IEE Proceedings -- Computers & Digital Techniques, 147, 159–165. https://doi.org/10.1049/ip-cdt:20000496
LibreCat
| DOI
2000 | Journal Article | LibreCat-ID: 10725
Platzner, M., Rinner, B., & Weiss, R. (2000). Toward embedded qualitative simulation: a specialized computer architecture for QSim. IEEE Intelligent Systems, 15(2), 62–68. https://doi.org/10.1109/5254.850829
LibreCat
| DOI
2000 | Conference Paper | LibreCat-ID: 13609
Eisenring, M. H., & Platzner, M. (2000). An Implementation Framework for Run-time Reconfigurable Systems. In Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE) (pp. 151–157). CSREA Press.
LibreCat
2000 | Conference Paper | LibreCat-ID: 13610
Eisenring, M., & Platzner, M. (2000). Optimization of Run-time Reconfigurable Embedded Systems. In Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL) (pp. 565–574). Springer.
LibreCat
1999 | Conference Paper | LibreCat-ID: 13607
Mencer, O., & Platzner, M. (1999). Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment. In Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32). IEEE CS Press. https://doi.org/10.1109/hicss.1999.772883
LibreCat
| DOI
1999 | Conference Paper | LibreCat-ID: 13608
Eisenring, M., Platzner, M., & Thiele, L. (1999). Communication Synthesis for Reconfigurable Embedded Systems. In Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL) (Vol. 1673, pp. 205–214). Springer. https://doi.org/10.1007/978-3-540-48302-1_21
LibreCat
| DOI
1998 | Journal Article | LibreCat-ID: 10607
Platzner, M. (1998). Reconfigurable Computer Architectures. E&i Elektrotechnik Und Informationstechnik, 115, 143–148.
LibreCat
1998 | Journal Article | LibreCat-ID: 10608
Platzner, M., & Rinner, B. (1998). Design and Implementation of a Parallel Constraint Satisfaction Algorithm. International Journal of Computers & Their Applications, 5, 106–116.
LibreCat
1998 | Misc | LibreCat-ID: 13464
Platzner, M., Rinner, B., & Weiss, R. (1998). A Distributed Computer Architecture for Fast Qualitative Simulation (pp. 106–107). Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities.
LibreCat
1998 | Conference Paper | LibreCat-ID: 13606
Platzner, M., & De Micheli, G. (1998). Acceleration of satisfiability algorithms by reconfigurable hardware. In Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) (pp. 69–78). Berlin, Heidelberg: Springer . https://doi.org/10.1007/bfb0055234
LibreCat
| DOI
1997 | Journal Article | LibreCat-ID: 10609
Platzner, M., Rinner, B., & Weiss, R. (1997). A Computer Architecture to Support Qualitative Simulation in Industrial Applications. E & i Elektrotechnik Und Informationstechnik, 114, 13–18.
LibreCat
1997 | Journal Article | LibreCat-ID: 10724
Platzner, M., Rinner, B., & Weiss, R. (1997). Parallel qualitative simulation. Simulation Practice and Theory, 5(7–8), 623–638. https://doi.org/10.1016/s0928-4869(97)00008-6
LibreCat
| DOI
1997 | Conference Paper | LibreCat-ID: 13603
Platzner, M., & Peters, L. (1997). Fast Signature Segmentation on a Multi-DSP Architecture. In Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing (Vol. 3166).
LibreCat
1997 | Conference Paper | LibreCat-ID: 13604
Röwekamp, T., Platzner, M., & Peters, L. (1997). Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP. In Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT) (pp. 829–833).
LibreCat
1996 | Conference Paper | LibreCat-ID: 13602
Lind, E., Platzner, M., & Rinner, B. (1996). A Multi-DSP System with Dynamically Reconfigurable Processors. In Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT).
LibreCat
1995 | Journal Article | LibreCat-ID: 10610
Platzner, M., Rinner, B., & Weiss, R. (1995). Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation. J.UCS Journal of Universal Computer Science, 12, 811–820.
LibreCat
1995 | Conference Paper | LibreCat-ID: 13469
Platzner, M., Rinner, B., & Weiss, R. (1995). A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs. In Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing (pp. 311–318). IEEE CS Press.
LibreCat