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25 Publications


2021 | Bachelorsthesis | LibreCat-ID: 22216
Rehnen, J. W. (2021). Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib.
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2021 | Bachelorsthesis | LibreCat-ID: 22483
Brede, M. (2021). Implementation and Profiling of XCS in the Context of Embedded Systems. Paderborn: Paderborn University.
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2020 | Bachelorsthesis | LibreCat-ID: 20820
Thiele, S. (2020). Implementing Machine Learning Functions as PYNQ FPGA Overlays.
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2020 | Mastersthesis | LibreCat-ID: 20821
Jaganath, V. (2020). Extension and Evaluation of Python-based High-Level Synthesis Tool Flows.
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2020 | Mastersthesis | LibreCat-ID: 21324
Chandrakar, K. (2020). Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis.
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2020 | Bachelorsthesis | LibreCat-ID: 21432
Henke, L.-S. (2020). Evaluation of a ReconOS-ROS Combination based on a Video Processing Application.
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2020 | Mastersthesis | LibreCat-ID: 21433
Jentzsch, F. P. (2020). Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture.
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2019 | Mastersthesis | LibreCat-ID: 15920
Keerthipati, M. (2019). A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn.
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2019 | Mastersthesis | LibreCat-ID: 15874
Lienen, C. (n.d.). Implementing a Real-time System on a Platform FPGA operated with ReconOS. Universität Paderborn.
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2019 | Mastersthesis | LibreCat-ID: 14831
Sabu, N. S. (2019). FPGA Acceleration of String Search Techniques in Huge Data Sets. Paderborn University.
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2019 | Mastersthesis | LibreCat-ID: 14546
Hansmeier, T. (2019). Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn.
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2018 | Dissertation | LibreCat-ID: 3720
Ho, N. (2018). FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn. https://doi.org/10.17619/UNIPB/1-376
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2018 | Bachelorsthesis | LibreCat-ID: 3365
Schnuer, J.-P. (2018). Static Scheduling Algorithms for Heterogeneous Compute Nodes. Universität Paderborn.
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2018 | Bachelorsthesis | LibreCat-ID: 3366
Croce, M. (2018). Evaluation of OpenCL-based Compilation for FPGAs. Universität Paderborn.
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2017 | Bachelorsthesis | LibreCat-ID: 3580
Hansmeier, T. (2017). An FPGA Accelerator for Checking Resolution Proofs. Universität Paderborn.
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2017 | Mastersthesis | LibreCat-ID: 74
Knorr, C. (2017). OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten. Universität Paderborn.
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2017 | Mastersthesis | LibreCat-ID: 1157
Witschen, L. M. (2017). A Framework for the Synthesis of Approximate Circuits. Universität Paderborn.
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2015 | Bachelorsthesis | LibreCat-ID: 3364
Knorr, C. (2015). Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten. Universität Paderborn.
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2014 | Mastersthesis | LibreCat-ID: 10701
Koch, B. (2014). Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University.
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2014 | Mastersthesis | LibreCat-ID: 10744
Surmund, S. (2014). Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University.
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