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264 Publications
2024 | Conference Paper | LibreCat-ID: 45778
Luchterhandt L, Nellius T, Beck R, et al. Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells. In: MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“. VDE Verlag; 2024.
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2024 | Conference Paper | LibreCat-ID: 53579
Palomero Bernardo P, Schmid P, Bringmann O, et al. A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing. In: DATE 24 - Design Automation and Test in Europe. ; 2024.
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2023 | Conference Paper | LibreCat-ID: 45775
Luchterhandt L, Nellius T, Beck R, et al. Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture. In: MBMV 2023 - 26. Workshop "Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg. VDE Verlag; 2023.
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2023 | Conference Paper | LibreCat-ID: 45776
Ecker W, Krstic M, Ulbricht M, et al. Scale4Edge – Scaling RISC-V for Edge Applications. In: RISC-V Summit Europe 2023, Barcelona, Spain, June 2023. ; 2023.
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2023 | Conference Paper | LibreCat-ID: 48530
Müller W, Ulbricht M, Li L, Krstic M. Der TETRISC SoC - Ein resilientes Quad-Core System auf Pulpissimo-Basis. In: 5. ITG / GMM / GI -Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen . ; 2023.
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2023 | Conference Abstract | LibreCat-ID: 48961
Iftekhar M, Gowda H, Kneuper P, Sadiye B, Müller W, Scheytt C. A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology. In: 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS). ; 2023. doi:10.1109/BCICTS54660.2023.10310954
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2022 | Conference Paper | LibreCat-ID: 29302
Ecker W, Adelt P, Müller W, et al. The Scale4Edge RISC-V Ecosystem. In: In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022). ; 2022.
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2021 | Conference Paper | LibreCat-ID: 32125
Adelt P, Koppelmann B, Müller W, Scheytt C. Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. In: MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. VDE; 2021.
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2021 | Conference Paper | LibreCat-ID: 32132
Adelt P, Koppelmann B, Müller W, Scheytt C. QEMU zur Simulation von Worst-Case-Ausführungszeiten. In: MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. VDE; 2021.
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2021 | Conference Paper | LibreCat-ID: 23992
Adelt P, Koppelmann B, Müller W, Scheytt C. Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. In: Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021). ; 2021.
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2020 | Conference Paper | LibreCat-ID: 24027
Adelt P, Koppelmann B, Müller W, Scheytt C. A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures. In: MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. ; 2020.
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2019 | Conference Paper | LibreCat-ID: 24058
Koppelmann B, Adelt P, Müller W, Scheytt C. RISC-V Extensions for Bit Manipulation Instructions. In: 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS). ; 2019. doi:10.1109/PATMOS.2019.8862170
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2019 | Conference Paper | LibreCat-ID: 24060
Adelt P, Koppelmann B, Müller W, Scheytt C. Analyse sicherheitskritischer Software für RISC-V Prozessoren. In: MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019). ; 2019.
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2019 | Conference Paper | LibreCat-ID: 24061
Adelt P, Koppelmann B, Müller W, Scheytt C, Driessen B. QEMU for Dynamic Memory Analysis of Security Sensitive Software. In: 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019. ; 2019:32-34.
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2019 | Journal Article | LibreCat-ID: 24063
Adelt P, Koppelmann B, Müller W, Scheytt C. QEMU Support for RISC-V: Current State and Future Releases. 2nd International Workshop on RISC-V Research Activities. 2019;(Presentation).
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2019 | Book (Editor) | LibreCat-ID: 53596
Bringmann O, Ecker W, Müller W, Müller-Gridschneder D, eds. Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT.; 2019.
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2018 | Journal Article | LibreCat-ID: 24194
Adelt P, Koppelmann B, Müller W. Current and Future RISC-V Activities for Virtual Prototyping and Chip Design. International Workshop on RISC-V Research Activities. 2018;Presentation.
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2018 | Conference Paper | LibreCat-ID: 24196
Wu L, Hussain MK, Abughannam S, Müller W, Scheytt C, Ecker W. Analog fault simulation automation at schematic level with random sampling techniques. In: 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)) . IEEE; 2018. doi:10.1109/DTIS.2018.8368549
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2018 | Book (Editor) | LibreCat-ID: 53595
Bringmann O, Ecker W, Müller W, Müller-Gridschneder D, eds. Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT.; 2018.
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2017 | Conference Paper | LibreCat-ID: 24220
Adelt P, Koppelmann B, Müller W, Mueller-Gritschneder D, Kleinjohann B, Scheytt C. Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen. In: Tagungsband des Wissenschaftsforums Intelligente Technische Systeme. Verlagsschriftenreihe des Heinz Nixdorf Instituts; 2017. doi:10.17619/UNIPB/1-93
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