Please note that LibreCat no longer supports Internet Explorer versions 8 or 9 (or earlier).
We recommend upgrading to the latest Internet Explorer, Google Chrome, or Firefox.
264 Publications
2024 | Conference Paper | LibreCat-ID: 45778
Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells
L. Luchterhandt, T. Nellius, R. Beck, R. Dömer, P. Kneuper, W. Müller, B. Sadiye, in: MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, VDE Verlag, 2024.
LibreCat
| Files available
L. Luchterhandt, T. Nellius, R. Beck, R. Dömer, P. Kneuper, W. Müller, B. Sadiye, in: MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, VDE Verlag, 2024.
2024 | Conference Paper | LibreCat-ID: 53579
A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing
P. Palomero Bernardo, P. Schmid, O. Bringmann, M. Iftekhar, B. Sadiye, W. Müller, A. Koch, E. Jentsch, A. Sauer, I. Feldner, W. Ecker, in: DATE 24 - Design Automation and Test in Europe, 2024.
LibreCat
P. Palomero Bernardo, P. Schmid, O. Bringmann, M. Iftekhar, B. Sadiye, W. Müller, A. Koch, E. Jentsch, A. Sauer, I. Feldner, W. Ecker, in: DATE 24 - Design Automation and Test in Europe, 2024.
2023 | Conference Paper | LibreCat-ID: 45775
Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture
L. Luchterhandt, T. Nellius, R. Beck, R. Dömer, P. Kneuper, W. Müller, B. Sadiye, in: MBMV 2023 - 26. Workshop "Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg, VDE Verlag, 2023.
LibreCat
| Files available
L. Luchterhandt, T. Nellius, R. Beck, R. Dömer, P. Kneuper, W. Müller, B. Sadiye, in: MBMV 2023 - 26. Workshop "Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg, VDE Verlag, 2023.
2023 | Conference Paper | LibreCat-ID: 45776
Scale4Edge – Scaling RISC-V for Edge Applications
W. Ecker, M. Krstic, M. Ulbricht, A. Mauderer, E. Jentzsch, A. Koch, B. Koppelmann, W. Müller, B. Sadiye, N. Bruns, R. Drechsler, D. Müller-Gritschneder, J. Schlamelcher, K. Grüttner, J. Bormann, W. Kunz, R. Heckmann, G. Angst, R. Wimmer, B. Becker, T. Faller, P. Palomero Bernardo, O. Brinkmann, J. Partzsch, C. Mayr, in: RISC-V Summit Europe 2023, Barcelona, Spain, June 2023., 2023.
LibreCat
| Files available
W. Ecker, M. Krstic, M. Ulbricht, A. Mauderer, E. Jentzsch, A. Koch, B. Koppelmann, W. Müller, B. Sadiye, N. Bruns, R. Drechsler, D. Müller-Gritschneder, J. Schlamelcher, K. Grüttner, J. Bormann, W. Kunz, R. Heckmann, G. Angst, R. Wimmer, B. Becker, T. Faller, P. Palomero Bernardo, O. Brinkmann, J. Partzsch, C. Mayr, in: RISC-V Summit Europe 2023, Barcelona, Spain, June 2023., 2023.
2023 | Conference Paper | LibreCat-ID: 48530
Der TETRISC SoC - Ein resilientes Quad-Core System auf Pulpissimo-Basis
W. Müller, M. Ulbricht, L. Li, M. Krstic, in: 5. ITG / GMM / GI -Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen , 2023.
LibreCat
W. Müller, M. Ulbricht, L. Li, M. Krstic, in: 5. ITG / GMM / GI -Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen , 2023.
2023 | Conference Abstract | LibreCat-ID: 48961
A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology
M. Iftekhar, H. Gowda, P. Kneuper, B. Sadiye, W. Müller, C. Scheytt, in: 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2023.
LibreCat
| Files available
| DOI
M. Iftekhar, H. Gowda, P. Kneuper, B. Sadiye, W. Müller, C. Scheytt, in: 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2023.
2022 | Conference Paper | LibreCat-ID: 29302
The Scale4Edge RISC-V Ecosystem
W. Ecker, P. Adelt, W. Müller, R. Heckmann, M. Krstic, V. Herdt, R. Drechsler, G. Angst, R. Wimmer, A. Mauderer, R. Stahl, K. Emrich, D. Mueller-Gritschneder, B. Becker, P. Scholl, E. Jentzsch, J. Schlamelcher, K. Grüttner, P.P. Bernardo, O. Brinkmann, M. Damian, J. Oppermann, A. Koch, J. Bormann, J. Partzsch, C. Mayr, W. Kunz, in: In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022), 2022.
LibreCat
W. Ecker, P. Adelt, W. Müller, R. Heckmann, M. Krstic, V. Herdt, R. Drechsler, G. Angst, R. Wimmer, A. Mauderer, R. Stahl, K. Emrich, D. Mueller-Gritschneder, B. Becker, P. Scholl, E. Jentzsch, J. Schlamelcher, K. Grüttner, P.P. Bernardo, O. Brinkmann, M. Damian, J. Oppermann, A. Koch, J. Bormann, J. Partzsch, C. Mayr, W. Kunz, in: In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022), 2022.
2021 | Conference Paper | LibreCat-ID: 32125
Register and Instruction Coverage Analysis for Different RISC-V ISA Modules
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, Munich, DE, 2021.
LibreCat
| Files available
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, Munich, DE, 2021.
2021 | Conference Paper | LibreCat-ID: 32132
QEMU zur Simulation von Worst-Case-Ausführungszeiten
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, Munich, DE, 2021.
LibreCat
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, Munich, DE, 2021.
2021 | Conference Paper | LibreCat-ID: 23992
Register and Instruction Coverage Analysis for Different RISC-V ISA Modules
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021), 2021.
LibreCat
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021), 2021.
2020 | Conference Paper | LibreCat-ID: 24027
A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, Stuttgart, DE, 2020.
LibreCat
| Files available
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, Stuttgart, DE, 2020.
2019 | Conference Paper | LibreCat-ID: 24058
RISC-V Extensions for Bit Manipulation Instructions
B. Koppelmann, P. Adelt, W. Müller, C. Scheytt, in: 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Rhodos, Griechenland, 2019.
LibreCat
| Files available
| DOI
B. Koppelmann, P. Adelt, W. Müller, C. Scheytt, in: 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Rhodos, Griechenland, 2019.
2019 | Conference Paper | LibreCat-ID: 24060
Analyse sicherheitskritischer Software für RISC-V Prozessoren
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019), Kaiserslautern, DE, 2019.
LibreCat
| Files available
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019), Kaiserslautern, DE, 2019.
2019 | Conference Paper | LibreCat-ID: 24061
QEMU for Dynamic Memory Analysis of Security Sensitive Software
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, B. Driessen, in: 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019, Florence, Italy, 2019, pp. 32–34.
LibreCat
| Files available
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, B. Driessen, in: 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019, Florence, Italy, 2019, pp. 32–34.
2019 | Journal Article | LibreCat-ID: 24063
QEMU Support for RISC-V: Current State and Future Releases
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, 2nd International Workshop on RISC-V Research Activities (Presentation) (2019).
LibreCat
| Files available
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, 2nd International Workshop on RISC-V Research Activities (Presentation) (2019).
2019 | Book (Editor) | LibreCat-ID: 53596
Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT
O. Bringmann, W. Ecker, W. Müller, D. Müller-Gridschneder, eds., Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT, Florence, Italy, 2019.
LibreCat
O. Bringmann, W. Ecker, W. Müller, D. Müller-Gridschneder, eds., Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT, Florence, Italy, 2019.
2018 | Journal Article | LibreCat-ID: 24194
Current and Future RISC-V Activities for Virtual Prototyping and Chip Design
P. Adelt, B. Koppelmann, W. Müller, International Workshop on RISC-V Research Activities Presentation (2018).
LibreCat
| Files available
P. Adelt, B. Koppelmann, W. Müller, International Workshop on RISC-V Research Activities Presentation (2018).
2018 | Conference Paper | LibreCat-ID: 24196
Analog fault simulation automation at schematic level with random sampling techniques
L. Wu, M.K. Hussain, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)) , IEEE, Italy/Taormina, 2018.
LibreCat
| Files available
| DOI
L. Wu, M.K. Hussain, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)) , IEEE, Italy/Taormina, 2018.
2018 | Book (Editor) | LibreCat-ID: 53595
Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT
O. Bringmann, W. Ecker, W. Müller, D. Müller-Gridschneder, eds., Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT, Dresden, Germany, 2018.
LibreCat
O. Bringmann, W. Ecker, W. Müller, D. Müller-Gridschneder, eds., Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT, Dresden, Germany, 2018.
2017 | Conference Paper | LibreCat-ID: 24220
Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen
P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann, C. Scheytt, in: Tagungsband des Wissenschaftsforums Intelligente Technische Systeme, Verlagsschriftenreihe des Heinz Nixdorf Instituts, Germany, Paderborn, 2017.
LibreCat
| Files available
| DOI
P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann, C. Scheytt, in: Tagungsband des Wissenschaftsforums Intelligente Technische Systeme, Verlagsschriftenreihe des Heinz Nixdorf Instituts, Germany, Paderborn, 2017.