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264 Publications
2024 | Conference Paper | LibreCat-ID: 45778
Luchterhandt L, Nellius T, Beck R, et al. Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells. In: MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“. VDE Verlag; 2024.
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2024 | Conference Paper | LibreCat-ID: 53579
Palomero Bernardo P, Schmid P, Bringmann O, et al. A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing. In: DATE 24 - Design Automation and Test in Europe. ; 2024.
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2023 | Conference Paper | LibreCat-ID: 45775
Luchterhandt L, Nellius T, Beck R, et al. Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture. In: MBMV 2023 - 26. Workshop "Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg. VDE Verlag; 2023.
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2023 | Conference Paper | LibreCat-ID: 45776
Ecker W, Krstic M, Ulbricht M, et al. Scale4Edge – Scaling RISC-V for Edge Applications. In: RISC-V Summit Europe 2023, Barcelona, Spain, June 2023. ; 2023.
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2023 | Conference Paper | LibreCat-ID: 48530
Müller W, Ulbricht M, Li L, Krstic M. Der TETRISC SoC - Ein resilientes Quad-Core System auf Pulpissimo-Basis. In: 5. ITG / GMM / GI -Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen . ; 2023.
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2023 | Conference Abstract | LibreCat-ID: 48961
Iftekhar M, Gowda H, Kneuper P, Sadiye B, Müller W, Scheytt C. A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology. In: 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS). ; 2023. doi:10.1109/BCICTS54660.2023.10310954
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2022 | Conference Paper | LibreCat-ID: 29302
Ecker W, Adelt P, Müller W, et al. The Scale4Edge RISC-V Ecosystem. In: In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022). ; 2022.
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2021 | Conference Paper | LibreCat-ID: 32125
Adelt P, Koppelmann B, Müller W, Scheytt C. Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. In: MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. VDE; 2021.
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2021 | Conference Paper | LibreCat-ID: 32132
Adelt P, Koppelmann B, Müller W, Scheytt C. QEMU zur Simulation von Worst-Case-Ausführungszeiten. In: MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. VDE; 2021.
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2021 | Conference Paper | LibreCat-ID: 23992
Adelt P, Koppelmann B, Müller W, Scheytt C. Register and Instruction Coverage Analysis for Different RISC-V ISA Modules. In: Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021). ; 2021.
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2020 | Conference Paper | LibreCat-ID: 24027
Adelt P, Koppelmann B, Müller W, Scheytt C. A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures. In: MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop. ; 2020.
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2019 | Conference Paper | LibreCat-ID: 24058
Koppelmann B, Adelt P, Müller W, Scheytt C. RISC-V Extensions for Bit Manipulation Instructions. In: 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS). ; 2019. doi:10.1109/PATMOS.2019.8862170
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2019 | Conference Paper | LibreCat-ID: 24060
Adelt P, Koppelmann B, Müller W, Scheytt C. Analyse sicherheitskritischer Software für RISC-V Prozessoren. In: MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019). ; 2019.
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2019 | Conference Paper | LibreCat-ID: 24061
Adelt P, Koppelmann B, Müller W, Scheytt C, Driessen B. QEMU for Dynamic Memory Analysis of Security Sensitive Software. In: 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019. ; 2019:32-34.
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2019 | Journal Article | LibreCat-ID: 24063
Adelt P, Koppelmann B, Müller W, Scheytt C. QEMU Support for RISC-V: Current State and Future Releases. 2nd International Workshop on RISC-V Research Activities. 2019;(Presentation).
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2019 | Book (Editor) | LibreCat-ID: 53596
Bringmann O, Ecker W, Müller W, Müller-Gridschneder D, eds. Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT.; 2019.
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2018 | Journal Article | LibreCat-ID: 24194
Adelt P, Koppelmann B, Müller W. Current and Future RISC-V Activities for Virtual Prototyping and Chip Design. International Workshop on RISC-V Research Activities. 2018;Presentation.
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2018 | Conference Paper | LibreCat-ID: 24196
Wu L, Hussain MK, Abughannam S, Müller W, Scheytt C, Ecker W. Analog fault simulation automation at schematic level with random sampling techniques. In: 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)) . IEEE; 2018. doi:10.1109/DTIS.2018.8368549
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2018 | Book (Editor) | LibreCat-ID: 53595
Bringmann O, Ecker W, Müller W, Müller-Gridschneder D, eds. Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT.; 2018.
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2017 | Conference Paper | LibreCat-ID: 24220
Adelt P, Koppelmann B, Müller W, Mueller-Gritschneder D, Kleinjohann B, Scheytt C. Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen. In: Tagungsband des Wissenschaftsforums Intelligente Technische Systeme. Verlagsschriftenreihe des Heinz Nixdorf Instituts; 2017. doi:10.17619/UNIPB/1-93
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2017 | Conference Paper | LibreCat-ID: 24223
Wu L, Abughannam S, Müller W, Scheytt C, Ecker W. SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study. In: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES). ; 2017:68.
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2017 | Conference Paper | LibreCat-ID: 24224
Adelt P, Koppelmann B, Müller W, Kleinjohann B, Scheytt C. ANALISA - A Tool for Static Instruction Set Analysis. In: Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation. ; 2017.
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2017 | Conference Paper | LibreCat-ID: 24225
Adelt P, Koppelmann B, Müller W, Kleinjohann B, Scheytt C. An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries. In: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) . ; 2017:44.
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2016 | Conference Paper | LibreCat-ID: 24264
Adelt P, Koppelmann B, Müller W, Becker M, Kleinjohann B, Scheytt C. Fast Dynamic Fault Injection for Virtual Microcontroller Platforms. In: Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC). ; 2016. doi:10.1109/VLSI-SoC.2016.7753545
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2016 | Conference Paper | LibreCat-ID: 24263
Abughannam S, Wu L, Müller W, Scheytt C, Ecker W, Novello C. Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study. In: Analog 2016 - VDE. ; 2016.
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2015 | Conference Paper | LibreCat-ID: 24289
Müller W, Wu L, Scheytt C, Becker M, Schoenberg S. On the Correlation of HW Faults and SW Errors. In: Mueller-Gritschneder D, Müller W, Mitra S, eds. Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014). ; 2015.
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2015 | Book (Editor) | LibreCat-ID: 53590
Müller-Gridschneder D, Müller W, Mitra S, eds. Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems.; 2015.
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2014 | Conference Paper | LibreCat-ID: 25145
Becker M, Kuznik C, Müller W. Virtual Platforms for Model-Based Design of Dependable Cyber-Physical System Software. In: 17th Euromicro Conference on Digital Systems Design (DSD). ; 2014.
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2014 | Conference Paper | LibreCat-ID: 25155
Becker M, Kuznik C, Müller W. Fault Effect Modeling in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems. In: ACM/IEEE 5th International Conference on Cyber-Physical Systems. ; 2014.
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2014 | Conference Paper | LibreCat-ID: 25161
Koppelmann B, Becker M, Müller W. Portierung der TriCore-Architektur auf QEMU. In: 17. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2014) . ; 2014.
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2014 | Conference Paper | LibreCat-ID: 24305
Mischkalla F, Müller W. Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation. In: Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV). IEEE; 2014. doi:10.1109/SAMOS.2014.6893219
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2014 | Journal Article | LibreCat-ID: 24302
Koppelmann B, Messidat B, Becker M, Kuznik C, Müller W, Scheytt C. Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. Design and Verification Conference (DVCON EUROPE). Published online 2014.
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2014 | Journal Article | LibreCat-ID: 24309
Kuznik C, Müller W. Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure. Design, Automation and Test in Europe DATE, University Booth, Dresden. Published online 2014.
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2014 | Conference Paper | LibreCat-ID: 24311
Oetjens J-H, Becker M, Kuznik C, et al. Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges. In: Design Automation Conference (DAC). ; 2014. doi:10.1145/2593069.2602976
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2014 | Conference Paper | LibreCat-ID: 25120
Mischkalla F, Müller W. Architectural Low-Power Design Using Transaction-Based System Simulation. In: Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV). IEEE; 2014.
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2014 | Conference Paper | LibreCat-ID: 25146
Joy M tech. MM, Müller W, Rammig F-J. Source code annotated memory leak detection for soft real time embedded systems with resource constraints. In: 12th IEEE International Conference on Embedded Computing. ; 2014.
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2014 | Conference Paper | LibreCat-ID: 25144
Mischkalla F, Müller W. Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation. In: PATMOS 2014. ; 2014.
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2014 | Conference Paper | LibreCat-ID: 36918
Becker M, Kuznik C, Müller W. Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems. In: IEEE; 2014. doi:10.1109/ICCPS.2014.6843726
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2014 | Conference Paper | LibreCat-ID: 36917
Kuznik C, Müller W, Defo GB. An Assisted Single Source Verification Metric Model Code Generation Methodology. In: ; 2014.
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2014 | Conference Paper | LibreCat-ID: 25166
Kuznik C, Müller W. Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM. In: 26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen. ; 2014.
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2014 | Conference Paper | LibreCat-ID: 25163
Kuznik C, Defo BG, Müller W. Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung. In: 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) . ; 2014.
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2014 | Journal Article | LibreCat-ID: 25151
Kuznik C, Defo BG, Müller W. An Assisted Single Source Verification Metric Model Code Generation Methodology. Electronic System Level Synthesis Conference (ESLSyn). Published online 2014.
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2014 | Conference Paper | LibreCat-ID: 34585
Koppelmann B, Messidat B, Becker M, Müller W, Scheytt JC. Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. In: Proceedings of the Design and Verification Conference Europe (DVCON Europe). ; 2014.
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2014 | Journal Article | LibreCat-ID: 25164
Becker M, Müller W, Stroop J, Kiffmeier U. HeroeS - A Framework for Heterogeneous Software-Intensive System Design with SystemC. Design, Automation and Test in Europe DATE, University Booth, Dresden. Published online 2014.
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2013 | Conference Paper | LibreCat-ID: 25270
Joy M tech. MM, Müller W, Rammig F-J. Early Phase Memory Leak Detection in Embedded Software Designs with Virtual Memory Management Model. In: Proceedings of AVICPS 2013, Dez. 2013 IEEE Computer Society,. Linköping University Electronic Press; 2013.
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2013 | Conference Paper | LibreCat-ID: 25271
He D, Müller W. AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS. In: Proceedings of International Conference on Applied Computing (AC). ; 2013.
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2013 | Conference Paper | LibreCat-ID: 25284
Mischkalla F, Müller W. Efficient Power Intent Validation Using Loosely-Timed Simulation Models. In: 23rd International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep. 2013. ; 2013.
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2013 | Conference Paper | LibreCat-ID: 25291
Becker M, Kiffmeier U, Müller W. HeroeS: Virtual Platform Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time Architectures. In: 16th IEEE Computer Society Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing. ; 2013.
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2013 | Conference Paper | LibreCat-ID: 25606
Kuznik C, F. S. Oliveira M, Müller W. SystemC Verification Components - An enhanced OVM/UVM for SystemC. In: EdaWorkshop 13. ; 2013.
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2013 | Conference Paper | LibreCat-ID: 25612
Mischkalla F, Müller W. Funktionale Verifikation von Low-Power Designs unter Verwendung Virtueller Prototypen. In: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV). ; 2013.
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2013 | Conference Paper | LibreCat-ID: 25614
Kuznik C, F. S. Oliveira M, Müller W. SC OVM: An Advanced SystemC Library for OVM-based Verification. In: Open SANITAS SystemC Verification Workshop. ; 2013.
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2013 | Newspaper Article | LibreCat-ID: 25615
Engels G, Gerth C, Kleinjohann L, Kleinjohann B, Müller W. Informationstechnik spart Ressourcen. ForschungsForum Paderborn . 2013.
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2013 | Conference Paper | LibreCat-ID: 25620
Kuznik C, Oliveira MF, Defo B, Müller W. Systematic Application of UCIS to Improve the Automation on Verification Closure. In: Proceedings of DVCON. ; 2013.
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2013 | Conference Paper | LibreCat-ID: 25632
Klobedanz K, Jatzkowski J, Rettberg A, Müller W. Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks. In: International Embedded Systems Symposium (IESS) 2013. Springer; 2013.
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2013 | Journal Article | LibreCat-ID: 25740
He D, Müller W. A heuristic energy-aware approach for hard real-time systems on multi-core platforms. Microprocessors and Microsystems - Embedded Hardware Design 37(6-7). Published online 2013:845-857.
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2013 | Book Chapter | LibreCat-ID: 25743
Anacker H, Dellnitz M, Flaßkamp K, et al. Methods for the Design and Development. In: Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future. Springer-Verlag; 2013:187-356.
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2013 | Conference Paper | LibreCat-ID: 36919
Mischkalla F, Müller W. Efficient Power-Intent Validation Using “Loosely-Timed” Simulation Models: A Non-Invasive Approach. In: IEEE; 2013. doi:10.1109/PATMOS.2013.6662171
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2013 | Conference Paper | LibreCat-ID: 36920
He D, Müller W. An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors. In: Weghorn H, ed. Proceedings of the International Conference on Applied Computing (AC). ; 2013.
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2012 | Conference Paper | LibreCat-ID: 25744
Joy M tech. MM, Becker M, Mathews E, Müller W. Automated Source Code Annotation for Timing Analysis of Embedded Software. In: In Proceedings of Advanced Computing and Communications Conference 2012 (ADCOM 2012). IEEE; 2012.
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2012 | Conference Paper | LibreCat-ID: 25758
Becker M, Baldin D, Kuznik C, Joy M tech. MM, Xie T, Müller W. XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software. In: EMSOFT’12: Teenth ACM International Conference on Embedded Software 2012 Proceedings . ; 2012.
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2012 | Conference Paper | LibreCat-ID: 25761
Oliveira MF, Kuznik C, Le HM, et al. The System Verification Methodology for Advanced TLM Verification. In: CODES/ISSS ’12: Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Proceedings. ; 2012.
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2012 | Conference Paper | LibreCat-ID: 25767
He D, Müller W. A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms. In: 15th Euromicro Conference on Digital System Design (DSD). IEEE Xplore; 2012.
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2012 | Conference Paper | LibreCat-ID: 26022
Becker M, Kuznik C, Joy M tech. MM, Xie T, Müller W. Binary Mutation Testing Through Dynamic Translation. In: 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN). ; 2012.
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2012 | Conference Paper | LibreCat-ID: 26023
He D, Müller W. Enhanced Schedulability Analysis of Hard Real-Time Systems on Power Manageable Multi-Core Platforms. In: Third International Symposium on Advances in Embedded Systems and Applications (ESA-2012). IEEE Xplore; 2012.
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2012 | Conference Paper | LibreCat-ID: 26024
Radke S, Rülke S, Oliveira MF, et al. Compilation of Methodologies to Speed up the Verification Process at System Level. In: EdaWorkshop 12. ; 2012.
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2012 | Conference Paper | LibreCat-ID: 26031
He D, Müller W. Online Energy-Efficient Hard Real-Time Scheduling for Component Oriented Systems. In: 2012 IEEE 15th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC). IEEE Xplore; 2012.
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2012 | Conference Paper | LibreCat-ID: 26036
Oliveira MF, Kuznik C, Müller W, Ecker W, Esen V. A SystemC Library for Advanced TLM Verification. In: Proceeding of Design and Verification Conference (DVCON). ; 2012.
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2012 | Conference Paper | LibreCat-ID: 26079
Becker M, Gnokam Defo GB, Müller W, Fummi F, Pravadelli G, Vinco S. MOUSSE: scaling MOdelling and verification to complex heterogeneoUS embedded Systems Evolution. In: Design, Automation and Test in Europe (DATE 2012). ; 2012.
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2012 | Conference Paper | LibreCat-ID: 26080
Becker M, Kuznik C, Joy M tech. M, Xie T, Müller W. XEMU: A QEMU Based Binary Mutation Testing Framework. In: Design, Automation and Test in Europe DATE. ; 2012.
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2012 | Conference Paper | LibreCat-ID: 26092
Müller W, Becker M, Zabel H, Elfeky A, DiPasquale A. Virtual Prototyping of Cyber-Physical Systems. In: In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012. ; 2012.
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2012 | Book Chapter | LibreCat-ID: 26695
Vanderperren Y, Müller W, He D, Mischkalla F, Dahaene W. Extending UML for Electronic Systems Design: A Code Generation Perspective. In: Nicolescu G, O’Connor I, Piguet C, eds. Design Technology for Heterogeneous Embedded Systems. 1st Edition. Auflage. Springer Verlag; 2012:13-39.
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2012 | Conference Paper | LibreCat-ID: 36922
Klobedanz K, Müller W, Rettberg A. An Approach for Self-Reconfiguring and Fault-Tolerant Distributed Real-Time Systems. In: IEEE; 2012. doi:10.1109/ISORCW.2012.41
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2012 | Conference Paper | LibreCat-ID: 36921
Oliveira MF, Kuznik C, Müller W, Esen V, Ecker W. Towards an Enhanced UVM for SystemC. In: Proceedings of the Design & Verification Conference (DVCon). ; 2012.
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2012 | Conference Paper | LibreCat-ID: 36994
Xie T, Müller W, Letombe F. Mutation-Analysis Driven Functional Verification of a Soft Microprocessor. In: Proceedings of SOCC2012. IEEE; 2012. doi:10.1109/SOCC.2012.6398362
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2012 | Conference Paper | LibreCat-ID: 36997
Xie T, Müller W. An IP-XACT-TO-SystemC Model Generator for Mutation Analysis. In: Proceedings of the MeCoES’12. ; 2012.
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2012 | Journal Article | LibreCat-ID: 26038
Kuznik C, Oliveira MF, Müller W. SYSTEMC UVM VERIFICATION COMPONENTS. Design, Automation and Test in Europe DATE. Published online 2012.
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2012 | Book (Editor) | LibreCat-ID: 53593
Müller W, Ecker W, eds. Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs .; 2012.
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2011 | Conference Paper | LibreCat-ID: 26667
Kuznik C, Müller W. Aspect enhanced functional coverage driven verification in the SystemC HDVL. In: Proc. of the 8th International SoC Design Conference 2011 (ISOCC 2011). ; 2011.
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2011 | Conference Paper | LibreCat-ID: 26669
Xie T, Müller W. IP-XACT based System Level Mutation Testing. In: Proceedings of the 16th IEEE International High Level Design Validation and Test Workshop (HLDVT). ; 2011.
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2011 | Conference Paper | LibreCat-ID: 26698
Xie T, Müller W. HDL-Mutation Based Simulation Data Generation by Propagation Guided Search. In: Proceedings of the 14th Euromicro Conference on Digital System Design (DSD). ; 2011.
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2011 | Journal Article | LibreCat-ID: 26705
Kuznik C, Müller W. Verification Closure of SystemC Designs with Functional Coverage. North American SystemC User Group Meeting (16th). Published online 2011.
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2011 | Conference Paper | LibreCat-ID: 26710
Becker M, Zabel H, Müller W, Elfeky A, DiPasquale A. Virtual Prototyping softwareintensiver mechatronischer Systeme Eine Fallstudie. In: 8. Paderborner Workshop Entwurf Mechatronischer Systeme, Band 294. Vol 294. Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn; 2011:315-327.
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2011 | Conference Paper | LibreCat-ID: 26713
Klobedanz K, König A, Müller W. A Reconfiguration Approach for Fault-Tolerant FlexRay Networks. In: Proceedings of Design, Automation, Test Europe - DATE2011. IEEE Computer Society Press; 2011.
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2011 | Conference Paper | LibreCat-ID: 26714
Klobedanz K, König A, Müller W, Rettberg A. Self-Reconfiguration for Fault-Tolerant FlexRay Networks. In: Second IEEE Workshop on Self-Organizing Real-Time Systems - SORT 2011. IEEE Computer Society Press; 2011.
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2011 | Conference Paper | LibreCat-ID: 26715
Kuznik C, Müller W. Functional Coverage-driven Verification with SystemC on Multiple Level of Abstraction. In: Proceedings of DVCON . ; 2011.
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2011 | Conference Paper | LibreCat-ID: 26716
Mischkalla F, He D, Müller W. A Retargetable SysML-based Front-End for High-Level Synthesis. In: Proceedings of 2nd Workshop on Model Based Engineering for Embedded Systems Design (M-BED). ; 2011.
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2011 | Conference Paper | LibreCat-ID: 26717
He D, Mischkalla F, Müller W. A SysML-based Framework with QEMU-SystemC Code Generation. In: Proceedings of 1st International QEMU Users Forum. ; 2011.
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2011 | Conference Paper | LibreCat-ID: 26784
Gnokam Defo GB, Müller W. Synchronisation eines SystemC Restbus-Simulators mit einem Hardware-In-the-Loop FlexRay Netzwerk. In: Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV). ; 2011.
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2011 | Conference Paper | LibreCat-ID: 26789
Kuznik C, Müller W. Native binary mutation analysis for embedded software and virtual prototypes in SystemC. In: Proceedings of the 17th IEEE Pacific Rim International Symposium on Dependable Computing. ; 2011.
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2011 | Conference Paper | LibreCat-ID: 37001
Becker M, Zabel H, Müller W, Elfeky A. Virtual Prototyping software-intensiver mechatronischer Systeme - Eine Fallstudie. In: ; 2011.
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2011 | Conference Paper | LibreCat-ID: 37005
Kuznik C, Müller W. A SystemC Based Library for Functional Coverage. In: ; 2011.
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2011 | Conference Paper | LibreCat-ID: 37006
Klobedanz K, König A, Müller W. A Reconfiguration Approach for Faul-Tolerant FlexRay Networks. In: Proceedings of DATE’11. IEEE; 2011. doi:10.1109/DATE.2011.5763022
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2011 | Book (Editor) | LibreCat-ID: 53580
Müller W, Petrot F, eds. Proceedings of the 1st International QEMU Users’ Forum.; 2011.
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2010 | Conference Paper | LibreCat-ID: 37007
Mischkalla F, He D, Müller W. Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems. In: Proceedings of DATE’10. IEEE; 2010. doi:10.1109/DATE.2010.5456990
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2010 | Conference Paper | LibreCat-ID: 37009
Oliveira MFS, Zabel H, Müller W. Assertion-Based Verification of RTOS Properties. In: Proceedings of DATE’10. IEEE; 2010. doi:10.1109/DATE.2010.5457130
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2010 | Conference Paper | LibreCat-ID: 37011
Klobedanz K, Kuznik C, Thuy A, Müller W. Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study. In: Proceedings of DATE’10, Dresden. IEEE; 2010. doi:10.1109/DATE.2010.5457125
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2010 | Conference Paper | LibreCat-ID: 37037
Krupp A, Müller W. A Systematic Approach to Combined HW/SW System Test. In: Proceedings of DATE’10. IEEE; 2010. doi:10.1109/DATE.2010.5457186
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2010 | Conference Paper | LibreCat-ID: 37040
Becker M, Di Guglielmo G, Fummi F, Müller W, Pravadelli G, Xie T. RTOS-Aware Refinement for TLM2.0-based HW/SW Design. In: Proceedings of DATE’10. IEEE; 2010. doi:10.1109/DATE.2010.5456965
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2010 | Conference Paper | LibreCat-ID: 37046
Becker M, Zabel H, Müller W. A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement. In: Kleinjohann L, Kleinjohann B, eds. Springer Verlag; 2010. doi:10.1007/978-3-642-15234-4_15
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| DOI
2010 | Conference Paper | LibreCat-ID: 37044
Klobedanz K, Defo GB, Zabel H, Müller W, Zhi Y. Task Migration for Fault-Tolerant FlexRay Networks. In: Kleinjohann L, Kleinjohann B, eds. Springer Verlag; 2010. doi:10.1007/978-3-642-15234-4_7
LibreCat
| DOI