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151 Publications
1995 | Report | LibreCat-ID: 13026
Hellebrand, S., & Wunderlich, H.-J. (1995). Synthesis Procedures for Self-Testable Controllers. University of Siegen, Germany.
LibreCat
1995 | Report | LibreCat-ID: 13027
Hellebrand, S., Wunderlich, H.-J., Goncalves, F., & Paulo Teixeira, J. (1995). Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. University Siegen, Germany.
LibreCat
1995 | Report | LibreCat-ID: 13028
Hellebrand, S., Herzog, M., & Wunderlich, H.-J. (1995). Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. University of Siegen, Germany.
LibreCat
1995 | Misc | LibreCat-ID: 13086
Hellebrand, S., Reeb, B., Tarnick, S., & Wunderlich, H.-J. (1995). Pattern Generation for a Deterministic BIST Scheme. 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA.
LibreCat
1995 | Journal Article | LibreCat-ID: 13011
Hellebrand, S., Rajski, J., Tarnick, S., Venkataraman, S., & Courtois, B. (1995). Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Transactions on Computers, 44(2), 223–233. https://doi.org/10.1109/12.364534
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| DOI
1995 | Conference Paper | LibreCat-ID: 13012
Hellebrand, S., Reeb, B., Tarnick, S., & Wunderlich, H.-J. (1995). Pattern Generation for a Deterministic BIST Scheme. ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), 88–94. https://doi.org/10.1109/iccad.1995.479997
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| DOI
1994 | Report | LibreCat-ID: 13024
Hellebrand, S., Juergensen, A., & Wunderlich, H.-J. (1994). Synthesis for Off-line Testability. University of Siegen, Germany.
LibreCat
1994 | Report | LibreCat-ID: 13025
Hellebrand, S., Juergensen, A., Stroele, A., & Wunderlich, H.-J. (1994). Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. University of Siegen, Germany.
LibreCat
1994 | Misc | LibreCat-ID: 13083
Venkataraman, S., Rajski, J., Hellebrand, S., & Tarnick, S. (1994). Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands.
LibreCat
1994 | Misc | LibreCat-ID: 13084
Hellebrand, S., & Wunderlich, H.-J. (1994). Ein Verfahren zur testfreundlichen Steuerwerkssynthese. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands.
LibreCat
1994 | Misc | LibreCat-ID: 13085
Hellebrand, S., Paulo Teixeira, J., & Wunderlich, H.-J. (1994). Synthesis for Testability - the ARCHIMEDES Approach. 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA.
LibreCat
1994 | Conference Paper | LibreCat-ID: 13014
Hellebrand, S., & Wunderlich, H.-J. (1994). An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures. ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), 110–116. https://doi.org/10.1109/iccad.1994.629752
LibreCat
| DOI
1994 | Conference Paper | LibreCat-ID: 13059
Hellebrand, S., & Wunderlich, H.-J. (1994). Synthese schneller selbsttestbarer Steuerwerke. Tagungsband Der GI/GME/ITG-Fachtagung \& Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme, 3–11.
LibreCat
1994 | Conference Paper | LibreCat-ID: 13013
Hellebrand, S., & Wunderlich, H.-J. (1994). Synthesis of Self-Testable Controllers. European Design and Test Conference (EDAC/ETC/EUROASIC), 580–585. https://doi.org/10.1109/edtc.1994.326815
LibreCat
| DOI
1993 | Misc | LibreCat-ID: 13081
Hellebrand, S., Tarnick, S., Rajski, J., & Courtois, B. (1993). Effiziente Erzeugung deterministischer Muster im Selbsttest. 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany.
LibreCat
1993 | Misc | LibreCat-ID: 13082
Hellebrand, S., & Wunderlich, H.-J. (1993). Synthesis of Self-Testable Controllers. ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France.
LibreCat
1993 | Conference Paper | LibreCat-ID: 13015
Venkataraman, S., Rajski, J., Hellebrand, S., & Tarnick, S. (1993). An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers. ACM/IEEE International Conference on Computer Aided Design (ICCAD’93). https://doi.org/10.1109/iccad.1993.580117
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| DOI
1992 | Report | LibreCat-ID: 13023
Hellebrand, S., Tarnick, S., Rajski, J., & Courtois, B. (1992). Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. Institut National Polytechnique de Grenoble, Grenoble, France.
LibreCat
1992 | Misc | LibreCat-ID: 13076
Hellebrand, S., Tarnick, S., Rajski, J., & Courtois, B. (1992). Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. IEEE Design for Testability Workshop, Vail, CO, USA.
LibreCat
1992 | Misc | LibreCat-ID: 13080
Hellebrand, S., Tarnick, S., Rajski, J., & Courtois, B. (1992). Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. Workshop on New Directions for Testing, Montreal, Canada.
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