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38 Publications
2023 | Journal Article | LibreCat-ID: 45361 |
R. Schade, T. Kenter, H. Elgabarty, M. Lass, T. Kühne, and C. Plessl, “Breaking the exascale barrier for the electronic structure problem in ab-initio molecular dynamics,” The International Journal of High Performance Computing Applications, Art. no. 109434202311776, 2023, doi: 10.1177/10943420231177631.
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2023 | Journal Article | LibreCat-ID: 46264
S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Workload-Aware Periodic Interconnect BIST,” IEEE Design &Test, pp. 1–1, 2023, doi: 10.1109/mdat.2023.3298849.
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2022 | Dissertation | LibreCat-ID: 29769 |
Q. A. Ahmed, Hardware Trojans in Reconfigurable Computing. Paderborn: Paderborn University, Paderborn, Germany, 2022.
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2022 | Journal Article | LibreCat-ID: 45847
J. Kontinen, A. Meier, and Y. Mahmood, “A parameterized view on the complexity of dependence and independence logic,” Journal of Logic and Computation, vol. 32, no. 8, pp. 1624–1644, 2022, doi: 10.1093/logcom/exac070.
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2022 | Journal Article | LibreCat-ID: 33684 |
R. Schade et al., “Towards electronic structure-based ab-initio molecular dynamics simulations with hundreds of millions of atoms,” Parallel Computing, vol. 111, Art. no. 102920, 2022, doi: 10.1016/j.parco.2022.102920.
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2021 | Dissertation | LibreCat-ID: 26746 |
T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware. Paderborn: Paderborn University, 2021.
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2021 | Journal Article | LibreCat-ID: 30907
A. Rodriguez, A. Otero, M. Platzner, and E. De la Torre, “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs,” IEEE Transactions on Computers, pp. 1–1, 2021, doi: 10.1109/tc.2021.3107196.
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2021 | Journal Article | LibreCat-ID: 27841
M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, and T. Wiersema, “Software/Hardware Co-Verification for Custom Instruction Set Processors,” IEEE Access, 2021, doi: 10.1109/ACCESS.2021.3131213.
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2020 | Journal Article | LibreCat-ID: 45845
Y. Mahmood, A. Meier, and J. Schmidt, “Parameterized complexity of abduction in Schaefer’s framework,” Journal of Logic and Computation, vol. 31, no. 1, pp. 266–296, 2020, doi: 10.1093/logcom/exaa079.
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2018 | Bachelorsthesis | LibreCat-ID: 1097
F. P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn, 2018.
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2017 | Conference Paper | LibreCat-ID: 10676
N. Ho, P. Kaufmann, and M. Platzner, “Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor,” in 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.
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2017 | Conference Paper | LibreCat-ID: 10780
Z. Guettatfi, P. Hübner, M. Platzner, and B. Rinner, “Computational self-awareness as design approach for visual sensor nodes,” in 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8.
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2016 | Conference Paper | LibreCat-ID: 15873
A. Boschmann, A. Agne, L. M. Witschen, G. Thombansen, F. Kraus, and M. Platzner, “FPGA-based acceleration of high density myoelectric signal processing,” in 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Mexiko City, Mexiko, 2016.
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2015 | Journal Article | LibreCat-ID: 39479
F. Vidor, T. Meyers, and U. Hilleringmann, “Flexible Electronics: Integration Processes for Organic and Inorganic Semiconductor-Based Thin-Film Transistors,” Electronics, vol. 4, no. 3, pp. 480–506, 2015, doi: 10.3390/electronics4030480.
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2014 | Journal Article | LibreCat-ID: 46266
B. Alizadeh, P. Behnam, and S. Sadeghi-Kohan, “A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs,” IEEE Transactions on Computers, pp. 1–1, 2014, doi: 10.1109/tc.2014.2329687.
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2012 | Conference Paper | LibreCat-ID: 36994
T. Xie, W. Müller, and F. Letombe, “Mutation-Analysis Driven Functional Verification of a Soft Microprocessor,” 2012, doi: 10.1109/SOCC.2012.6398362.
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