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43 Publications
2014 | Journal Article | LibreCat-ID: 46266
B. Alizadeh, P. Behnam, and S. Sadeghi-Kohan, “A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs,” IEEE Transactions on Computers, pp. 1–1, 2014, doi: 10.1109/tc.2014.2329687.
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2012 | Conference Paper | LibreCat-ID: 36994
T. Xie, W. Müller, and F. Letombe, “Mutation-Analysis Driven Functional Verification of a Soft Microprocessor,” 2012, doi: 10.1109/SOCC.2012.6398362.
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2011 | Conference Paper | LibreCat-ID: 37002
T. Xie, W. Müller, and F. Letombe, “HDL-Mutation Based Simulation Data Generation by Propagation Guided Search,” 2011, doi: 10.1109/DSD.2011.83.
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2010 | Conference Paper | LibreCat-ID: 37009
M. F. S. Oliveira, H. Zabel, and W. Müller, “Assertion-Based Verification of RTOS Properties,” presented at the 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden, 2010, doi: 10.1109/DATE.2010.5457130.
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2010 | Conference Paper | LibreCat-ID: 37011
K. Klobedanz, C. Kuznik, A. Thuy, and W. Müller, “Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study,” presented at the 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden, 2010, doi: 10.1109/DATE.2010.5457125.
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2010 | Conference Paper | LibreCat-ID: 37040
M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie, “RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden, 2010, doi: 10.1109/DATE.2010.5456965.
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2010 | Conference Paper | LibreCat-ID: 37053
W. Müller, M. F. da S. Oliveira, H. Zabel, and M. Becker, “Verification of Real-Time Properties for Hardware-Dependant Software,” presented at the IEEE International High Level Design Validation and Test Workshop (HLDVT), Anaheim, FL, USA, 2010.
LibreCat
2010 | Conference Paper | LibreCat-ID: 37039
M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie, “RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden, 2010, doi: 10.1109/DATE.2010.5456965.
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2009 | Conference Paper | LibreCat-ID: 2262
P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2009, pp. 11–18.
LibreCat
2006 | Conference Paper | LibreCat-ID: 38107
J. Großmann and W. Müller, “A Formal Behavioral Semantics for TestML,” Paphos, Cyprus, 2006, doi: 10.1109/ISoLA.2006.37.
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2005 | Conference Paper | LibreCat-ID: 39029
T. Schattkowsky, W. Müller, and A. Rettberg, “A Model-Based Approach for Executable Specification on Reconfigurable Hardware,” 2005, doi: 10.1109/DATE.2005.20.
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2005 | Conference Paper | LibreCat-ID: 39030
T. Schattkowsky and W. Müller, “A UML Virtual Machine for Embedded Systems,” 2005.
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2005 | Conference Paper | LibreCat-ID: 39032
T. Schattkowsky and W. Müller, “Transformation of UML State Machines for Direct Execution,” 2005, doi: 10.1109/VLHCC.2005.64.
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2004 | Conference Paper | LibreCat-ID: 2415
C. Plessl and M. Platzner, “Virtualization of Hardware – Introduction and Survey,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2004, pp. 63–69.
LibreCat
2002 | Journal Article | LibreCat-ID: 39925
K. Goser, U. Hilleringmann, U. Rueckert, and K. Schumacher, “VLSI technologies for artificial neural networks,” IEEE Micro, vol. 9, no. 6, pp. 28–44, 2002, doi: 10.1109/40.42985.
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2002 | Journal Article | LibreCat-ID: 39926
K. Goser, U. Hilleringmann, U. Rueckert, and K. Schumacher, “VLSI technologies for artificial neural networks,” IEEE Micro, vol. 9, no. 6, pp. 28–44, 2002, doi: 10.1109/40.42985.
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