7 Publications

Mark all

[7]
2020 | Conference Paper | LibreCat-ID: 19422
Sprenger, A., Sadeghi-Kohan, S., Reimer, J. D., & Hellebrand, S. (n.d.). Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020. Virtual Conference - Originally Frascati (Rome), Italy.
LibreCat
 
[6]
2020 | Conference Paper | LibreCat-ID: 19421
Holst, S., Kampmann, M., Sprenger, A., Reimer, J. D., Hellebrand, S., Wunderlich, H.-J., & Weng, X. (n.d.). Logic Fault Diagnosis of Hidden Delay Defects. In IEEE International Test Conference (ITC’20), November 2020. Virtual Conference - Originally Washington, DC.
LibreCat
 
[5]
2019 | Misc | LibreCat-ID: 8112
Maaz, M. U., Sprenger, A., & Hellebrand, S. (2019). A Hybrid Space Compactor for Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19).
LibreCat
 
[4]
2019 | Journal Article | LibreCat-ID: 8667
Sprenger, A., & Hellebrand, S. (2019). Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. Journal of Circuits, Systems and Computers, 28(1), 1–23. https://doi.org/10.1142/s0218126619400012
LibreCat | DOI
 
[3]
2019 | Conference Paper | LibreCat-ID: 12918
Maaz, M. U., Sprenger, A., & Hellebrand, S. (2019). A Hybrid Space Compactor for Adaptive X-Handling. In 50th IEEE International Test Conference (ITC) (pp. 1–8). Washington, DC, USA: IEEE.
LibreCat
 
[2]
2018 | Misc | LibreCat-ID: 4576
Sprenger, A., & Hellebrand, S. (2018). Stochastische Kompaktierung für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18).
LibreCat
 
[1]
2018 | Conference Paper | LibreCat-ID: 4575
Sprenger, A., & Hellebrand, S. (2018). Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. In 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Budapest: IEEE. https://doi.org/10.1109/ddecs.2018.00020
LibreCat | DOI
 

Search

Filter Publications

Display / Sort

Citation Style: APA

Export / Embed

7 Publications

Mark all

[7]
2020 | Conference Paper | LibreCat-ID: 19422
Sprenger, A., Sadeghi-Kohan, S., Reimer, J. D., & Hellebrand, S. (n.d.). Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020. Virtual Conference - Originally Frascati (Rome), Italy.
LibreCat
 
[6]
2020 | Conference Paper | LibreCat-ID: 19421
Holst, S., Kampmann, M., Sprenger, A., Reimer, J. D., Hellebrand, S., Wunderlich, H.-J., & Weng, X. (n.d.). Logic Fault Diagnosis of Hidden Delay Defects. In IEEE International Test Conference (ITC’20), November 2020. Virtual Conference - Originally Washington, DC.
LibreCat
 
[5]
2019 | Misc | LibreCat-ID: 8112
Maaz, M. U., Sprenger, A., & Hellebrand, S. (2019). A Hybrid Space Compactor for Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19).
LibreCat
 
[4]
2019 | Journal Article | LibreCat-ID: 8667
Sprenger, A., & Hellebrand, S. (2019). Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. Journal of Circuits, Systems and Computers, 28(1), 1–23. https://doi.org/10.1142/s0218126619400012
LibreCat | DOI
 
[3]
2019 | Conference Paper | LibreCat-ID: 12918
Maaz, M. U., Sprenger, A., & Hellebrand, S. (2019). A Hybrid Space Compactor for Adaptive X-Handling. In 50th IEEE International Test Conference (ITC) (pp. 1–8). Washington, DC, USA: IEEE.
LibreCat
 
[2]
2018 | Misc | LibreCat-ID: 4576
Sprenger, A., & Hellebrand, S. (2018). Stochastische Kompaktierung für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18).
LibreCat
 
[1]
2018 | Conference Paper | LibreCat-ID: 4575
Sprenger, A., & Hellebrand, S. (2018). Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. In 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Budapest: IEEE. https://doi.org/10.1109/ddecs.2018.00020
LibreCat | DOI
 

Search

Filter Publications

Display / Sort

Citation Style: APA

Export / Embed