6 Publications
2026 | Conference Paper | LibreCat-ID: 63758
Hannemann, Kai Arne, Lars Luchterhandt, Wolfgang Müller, Markus Ulbricht, and Li Lu. “Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations.” In 38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen. Potsdam, 2026.
LibreCat
2026 | Conference Paper | LibreCat-ID: 65595
Hannemann, Kai Arne, Lars Luchterhandt, Wolfgang Müller, Markus Ulbricht, Li Lu, and J. Christoph Scheytt. “TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture.” In 29. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2026), 2026.
LibreCat
2025 | Conference Paper | LibreCat-ID: 58861
Luchterhandt, Lars, Vivek Govindasamy, Yutong Wang, Rainer Dömer, Wolfgang Müller, and J. Christoph Scheytt. “Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells.” In OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits. Lyon, France, 2025.
LibreCat
2025 | Conference Paper | LibreCat-ID: 66520
Luchterhandt, Lars, Vivek Govindasamy, Yutong Wang, Christoph Scheytt, Wolfgang Müller, and Rainer Dömer. “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids.” In 2025 Forum on Specification &Amp; Design Languages (FDL). IEEE, 2025. https://doi.org/10.1109/fdl68117.2025.11165408.
LibreCat
| DOI
2024 | Conference Paper | LibreCat-ID: 45778
Luchterhandt, Lars, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper, Wolfgang Müller, and Babak Sadiye. “Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells.” In MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“. VDE Verlag, 2024.
LibreCat
2023 | Conference Paper | LibreCat-ID: 45775
Luchterhandt, Lars, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper, Wolfgang Müller, and Babak Sadiye. “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture.” In MBMV 2023 - 26. Workshop "Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg. VDE Verlag, 2023.
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6 Publications
2026 | Conference Paper | LibreCat-ID: 63758
Hannemann, Kai Arne, Lars Luchterhandt, Wolfgang Müller, Markus Ulbricht, and Li Lu. “Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations.” In 38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen. Potsdam, 2026.
LibreCat
2026 | Conference Paper | LibreCat-ID: 65595
Hannemann, Kai Arne, Lars Luchterhandt, Wolfgang Müller, Markus Ulbricht, Li Lu, and J. Christoph Scheytt. “TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture.” In 29. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2026), 2026.
LibreCat
2025 | Conference Paper | LibreCat-ID: 58861
Luchterhandt, Lars, Vivek Govindasamy, Yutong Wang, Rainer Dömer, Wolfgang Müller, and J. Christoph Scheytt. “Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells.” In OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits. Lyon, France, 2025.
LibreCat
2025 | Conference Paper | LibreCat-ID: 66520
Luchterhandt, Lars, Vivek Govindasamy, Yutong Wang, Christoph Scheytt, Wolfgang Müller, and Rainer Dömer. “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids.” In 2025 Forum on Specification &Amp; Design Languages (FDL). IEEE, 2025. https://doi.org/10.1109/fdl68117.2025.11165408.
LibreCat
| DOI
2024 | Conference Paper | LibreCat-ID: 45778
Luchterhandt, Lars, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper, Wolfgang Müller, and Babak Sadiye. “Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells.” In MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“. VDE Verlag, 2024.
LibreCat
2023 | Conference Paper | LibreCat-ID: 45775
Luchterhandt, Lars, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper, Wolfgang Müller, and Babak Sadiye. “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture.” In MBMV 2023 - 26. Workshop "Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg. VDE Verlag, 2023.
LibreCat