6 Publications
2026 | Conference Paper | LibreCat-ID: 63758
K. A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, and L. Lu, “Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations,” presented at the 38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Potsdam, 2026.
LibreCat
2026 | Conference Paper | LibreCat-ID: 65595
K. A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, L. Lu, and J. C. Scheytt, “TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture,” presented at the 29. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2026), Würzburg, 2026.
LibreCat
2025 | Conference Paper | LibreCat-ID: 58861
L. Luchterhandt, V. Govindasamy, Y. Wang, R. Dömer, W. Müller, and J. C. Scheytt, “Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells,” 2025.
LibreCat
2025 | Conference Paper | LibreCat-ID: 66520
L. Luchterhandt, V. Govindasamy, Y. Wang, C. Scheytt, W. Müller, and R. Dömer, “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids,” 2025, doi: 10.1109/fdl68117.2025.11165408.
LibreCat
| DOI
2024 | Conference Paper | LibreCat-ID: 45778
L. Luchterhandt et al., “Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells,” presented at the MBMV 2023 - 26. Workshop, Freiburg, , Germany, Freiburg, 2024.
LibreCat
2023 | Conference Paper | LibreCat-ID: 45775
L. Luchterhandt et al., “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture,” presented at the MBMV 2023, Freiburg, Freiburg, 2023.
LibreCat
6 Publications
2026 | Conference Paper | LibreCat-ID: 63758
K. A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, and L. Lu, “Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations,” presented at the 38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Potsdam, 2026.
LibreCat
2026 | Conference Paper | LibreCat-ID: 65595
K. A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, L. Lu, and J. C. Scheytt, “TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture,” presented at the 29. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2026), Würzburg, 2026.
LibreCat
2025 | Conference Paper | LibreCat-ID: 58861
L. Luchterhandt, V. Govindasamy, Y. Wang, R. Dömer, W. Müller, and J. C. Scheytt, “Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells,” 2025.
LibreCat
2025 | Conference Paper | LibreCat-ID: 66520
L. Luchterhandt, V. Govindasamy, Y. Wang, C. Scheytt, W. Müller, and R. Dömer, “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids,” 2025, doi: 10.1109/fdl68117.2025.11165408.
LibreCat
| DOI
2024 | Conference Paper | LibreCat-ID: 45778
L. Luchterhandt et al., “Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells,” presented at the MBMV 2023 - 26. Workshop, Freiburg, , Germany, Freiburg, 2024.
LibreCat
2023 | Conference Paper | LibreCat-ID: 45775
L. Luchterhandt et al., “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture,” presented at the MBMV 2023, Freiburg, Freiburg, 2023.
LibreCat