6 Publications
2026 | Conference Paper | LibreCat-ID: 63758
@inproceedings{Hannemann_Luchterhandt_Müller_Ulbricht_Lu_2026, place={Potsdam}, title={Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations}, booktitle={38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen}, author={Hannemann, Kai Arne and Luchterhandt, Lars and Müller, Wolfgang and Ulbricht, Markus and Lu, Li}, year={2026} }
LibreCat
2026 | Conference Paper | LibreCat-ID: 65595
@inproceedings{Hannemann_Luchterhandt_Müller_Ulbricht_Lu_Scheytt_2026, title={TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture}, booktitle={29. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2026)}, author={Hannemann, Kai Arne and Luchterhandt, Lars and Müller, Wolfgang and Ulbricht, Markus and Lu, Li and Scheytt, J. Christoph}, year={2026} }
LibreCat
2025 | Conference Paper | LibreCat-ID: 58861
@inproceedings{Luchterhandt_Govindasamy_Wang_Dömer_Müller_Scheytt_2025, place={Lyon, France}, title={Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells}, booktitle={OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits}, author={Luchterhandt, Lars and Govindasamy, Vivek and Wang, Yutong and Dömer, Rainer and Müller, Wolfgang and Scheytt, J. Christoph}, year={2025} }
LibreCat
2025 | Conference Paper | LibreCat-ID: 66520
@inproceedings{Luchterhandt_Govindasamy_Wang_Scheytt_Müller_Dömer_2025, title={A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids}, DOI={10.1109/fdl68117.2025.11165408}, booktitle={2025 Forum on Specification & Design Languages (FDL)}, publisher={IEEE}, author={Luchterhandt, Lars and Govindasamy, Vivek and Wang, Yutong and Scheytt, Christoph and Müller, Wolfgang and Dömer, Rainer}, year={2025} }
LibreCat
| DOI
2024 | Conference Paper | LibreCat-ID: 45778
@inproceedings{Luchterhandt_Nellius_Beck_Dömer_Kneuper_Müller_Sadiye_2024, title={Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells}, booktitle={MBMV 2024 - 27. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“}, publisher={VDE Verlag}, author={Luchterhandt, Lars and Nellius, Tom and Beck, Robert and Dömer, Rainer and Kneuper, Pascal and Müller, Wolfgang and Sadiye, Babak}, year={2024} }
LibreCat
2023 | Conference Paper | LibreCat-ID: 45775
@inproceedings{Luchterhandt_Nellius_Beck_Dömer_Kneuper_Müller_Sadiye_2023, title={Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture}, booktitle={MBMV 2023 - 26. Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“, MBMV 2023, Freiburg}, publisher={VDE Verlag}, author={Luchterhandt, Lars and Nellius, Tom and Beck, Robert and Dömer, Rainer and Kneuper, Pascal and Müller, Wolfgang and Sadiye, Babak}, year={2023} }
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6 Publications
2026 | Conference Paper | LibreCat-ID: 63758
@inproceedings{Hannemann_Luchterhandt_Müller_Ulbricht_Lu_2026, place={Potsdam}, title={Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations}, booktitle={38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen}, author={Hannemann, Kai Arne and Luchterhandt, Lars and Müller, Wolfgang and Ulbricht, Markus and Lu, Li}, year={2026} }
LibreCat
2026 | Conference Paper | LibreCat-ID: 65595
@inproceedings{Hannemann_Luchterhandt_Müller_Ulbricht_Lu_Scheytt_2026, title={TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture}, booktitle={29. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2026)}, author={Hannemann, Kai Arne and Luchterhandt, Lars and Müller, Wolfgang and Ulbricht, Markus and Lu, Li and Scheytt, J. Christoph}, year={2026} }
LibreCat
2025 | Conference Paper | LibreCat-ID: 58861
@inproceedings{Luchterhandt_Govindasamy_Wang_Dömer_Müller_Scheytt_2025, place={Lyon, France}, title={Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells}, booktitle={OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits}, author={Luchterhandt, Lars and Govindasamy, Vivek and Wang, Yutong and Dömer, Rainer and Müller, Wolfgang and Scheytt, J. Christoph}, year={2025} }
LibreCat
2025 | Conference Paper | LibreCat-ID: 66520
@inproceedings{Luchterhandt_Govindasamy_Wang_Scheytt_Müller_Dömer_2025, title={A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids}, DOI={10.1109/fdl68117.2025.11165408}, booktitle={2025 Forum on Specification & Design Languages (FDL)}, publisher={IEEE}, author={Luchterhandt, Lars and Govindasamy, Vivek and Wang, Yutong and Scheytt, Christoph and Müller, Wolfgang and Dömer, Rainer}, year={2025} }
LibreCat
| DOI
2024 | Conference Paper | LibreCat-ID: 45778
@inproceedings{Luchterhandt_Nellius_Beck_Dömer_Kneuper_Müller_Sadiye_2024, title={Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells}, booktitle={MBMV 2024 - 27. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“}, publisher={VDE Verlag}, author={Luchterhandt, Lars and Nellius, Tom and Beck, Robert and Dömer, Rainer and Kneuper, Pascal and Müller, Wolfgang and Sadiye, Babak}, year={2024} }
LibreCat
2023 | Conference Paper | LibreCat-ID: 45775
@inproceedings{Luchterhandt_Nellius_Beck_Dömer_Kneuper_Müller_Sadiye_2023, title={Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture}, booktitle={MBMV 2023 - 26. Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“, MBMV 2023, Freiburg}, publisher={VDE Verlag}, author={Luchterhandt, Lars and Nellius, Tom and Beck, Robert and Dömer, Rainer and Kneuper, Pascal and Müller, Wolfgang and Sadiye, Babak}, year={2023} }
LibreCat