Truly Scalable Grids of RISC-V Processors with Local Memories

Massively parallel computer architectures based on identical microprocessor tiles are well known for their high scalability and performance. In this work, we introduce the design and simulation of a scalable on-chip grid of RISC-V processors with local memories in a structured EDA flow. We specify a Grid of Processing Cells (GPC) with two non-trivial software applications and successively generate and validate the hardware models at lower abstraction levels, namely TLM, ISS, RTL, and FPGA. Our comprehensive experimental evaluation of a physical implementation on an FPGA shows the true scalability of the GPC architecture. While existing works have indicated performance benefits for GPCs at high abstraction levels, our results confirm their highly reduced interconnect contention for the first time on fully constructed hardware with clock-cycle accuracy at RTL and on FPGAs.