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264 Publications


2024 | Conference Paper | LibreCat-ID: 45778
Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells
L. Luchterhandt, T. Nellius, R. Beck, R. Dömer, P. Kneuper, W. Müller, B. Sadiye, in: MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, VDE Verlag, 2024.
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2024 | Conference Paper | LibreCat-ID: 53579
A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing
P. Palomero Bernardo, P. Schmid, O. Bringmann, M. Iftekhar, B. Sadiye, W. Müller, A. Koch, E. Jentsch, A. Sauer, I. Feldner, W. Ecker, in: DATE 24 - Design Automation and Test in Europe, 2024.
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2023 | Conference Paper | LibreCat-ID: 45775
Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture
L. Luchterhandt, T. Nellius, R. Beck, R. Dömer, P. Kneuper, W. Müller, B. Sadiye, in: MBMV 2023 - 26. Workshop "Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg, VDE Verlag, 2023.
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2023 | Conference Paper | LibreCat-ID: 45776
Scale4Edge – Scaling RISC-V for Edge Applications
W. Ecker, M. Krstic, M. Ulbricht, A. Mauderer, E. Jentzsch, A. Koch, B. Koppelmann, W. Müller, B. Sadiye, N. Bruns, R. Drechsler, D. Müller-Gritschneder, J. Schlamelcher, K. Grüttner, J. Bormann, W. Kunz, R. Heckmann, G. Angst, R. Wimmer, B. Becker, T. Faller, P. Palomero Bernardo, O. Brinkmann, J. Partzsch, C. Mayr, in: RISC-V Summit Europe 2023, Barcelona, Spain, June 2023., 2023.
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2023 | Conference Paper | LibreCat-ID: 48530
Der TETRISC SoC - Ein resilientes Quad-Core System auf Pulpissimo-Basis
W. Müller, M. Ulbricht, L. Li, M. Krstic, in: 5. ITG / GMM / GI -Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen , 2023.
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2023 | Conference Abstract | LibreCat-ID: 48961
A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology
M. Iftekhar, H. Gowda, P. Kneuper, B. Sadiye, W. Müller, C. Scheytt, in: 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2023.
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2022 | Conference Paper | LibreCat-ID: 29302
The Scale4Edge RISC-V Ecosystem
W. Ecker, P. Adelt, W. Müller, R. Heckmann, M. Krstic, V. Herdt, R. Drechsler, G. Angst, R. Wimmer, A. Mauderer, R. Stahl, K. Emrich, D. Mueller-Gritschneder, B. Becker, P. Scholl, E. Jentzsch, J. Schlamelcher, K. Grüttner, P.P. Bernardo, O. Brinkmann, M. Damian, J. Oppermann, A. Koch, J. Bormann, J. Partzsch, C. Mayr, W. Kunz, in: In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022), 2022.
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2021 | Conference Paper | LibreCat-ID: 32125
Register and Instruction Coverage Analysis for Different RISC-V ISA Modules
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, Munich, DE, 2021.
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2021 | Conference Paper | LibreCat-ID: 32132
QEMU zur Simulation von Worst-Case-Ausführungszeiten
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, Munich, DE, 2021.
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2021 | Conference Paper | LibreCat-ID: 23992
Register and Instruction Coverage Analysis for Different RISC-V ISA Modules
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021), 2021.
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2020 | Conference Paper | LibreCat-ID: 24027
A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, Stuttgart, DE, 2020.
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2019 | Conference Paper | LibreCat-ID: 24058
RISC-V Extensions for Bit Manipulation Instructions
B. Koppelmann, P. Adelt, W. Müller, C. Scheytt, in: 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Rhodos, Griechenland, 2019.
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2019 | Conference Paper | LibreCat-ID: 24060
Analyse sicherheitskritischer Software für RISC-V Prozessoren
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, in: MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019), Kaiserslautern, DE, 2019.
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2019 | Conference Paper | LibreCat-ID: 24061
QEMU for Dynamic Memory Analysis of Security Sensitive Software
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, B. Driessen, in: 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019, Florence, Italy, 2019, pp. 32–34.
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2019 | Journal Article | LibreCat-ID: 24063
QEMU Support for RISC-V: Current State and Future Releases
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, 2nd International Workshop on RISC-V Research Activities (Presentation) (2019).
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2019 | Book (Editor) | LibreCat-ID: 53596
Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT
O. Bringmann, W. Ecker, W. Müller, D. Müller-Gridschneder, eds., Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT, Florence, Italy, 2019.
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2018 | Journal Article | LibreCat-ID: 24194
Current and Future RISC-V Activities for Virtual Prototyping and Chip Design
P. Adelt, B. Koppelmann, W. Müller, International Workshop on RISC-V Research Activities Presentation (2018).
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2018 | Conference Paper | LibreCat-ID: 24196
Analog fault simulation automation at schematic level with random sampling techniques
L. Wu, M.K. Hussain, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)) , IEEE, Italy/Taormina, 2018.
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2018 | Book (Editor) | LibreCat-ID: 53595
Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT
O. Bringmann, W. Ecker, W. Müller, D. Müller-Gridschneder, eds., Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT, Dresden, Germany, 2018.
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2017 | Conference Paper | LibreCat-ID: 24220
Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen
P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann, C. Scheytt, in: Tagungsband des Wissenschaftsforums Intelligente Technische Systeme, Verlagsschriftenreihe des Heinz Nixdorf Instituts, Germany, Paderborn, 2017.
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2017 | Conference Paper | LibreCat-ID: 24223
SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study
L. Wu, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES), Lausanne, Switzerland, 2017, p. 68.
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2017 | Conference Paper | LibreCat-ID: 24224
ANALISA - A Tool for Static Instruction Set Analysis
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, C. Scheytt, in: Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation, Lausanne, CH, 2017.
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2017 | Conference Paper | LibreCat-ID: 24225
An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, C. Scheytt, in: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) , Lausanne, Switzerland, 2017, p. 44.
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2016 | Conference Paper | LibreCat-ID: 24264
Fast Dynamic Fault Injection for Virtual Microcontroller Platforms
P. Adelt, B. Koppelmann, W. Müller, M. Becker, B. Kleinjohann, C. Scheytt, in: Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC), Tallin, Estonia, 2016.
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2016 | Conference Paper | LibreCat-ID: 24263
Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study
S. Abughannam, L. Wu, W. Müller, C. Scheytt, W. Ecker, C. Novello, in: Analog 2016 - VDE, 2016.
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2015 | Conference Paper | LibreCat-ID: 24289
On the Correlation of HW Faults and SW Errors
W. Müller, L. Wu, C. Scheytt, M. Becker, S. Schoenberg, in: D. Mueller-Gritschneder, W. Müller, S. Mitra (Eds.), Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014), Amsterdam, Netherland, 2015.
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2015 | Book (Editor) | LibreCat-ID: 53590
Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems
D. Müller-Gridschneder, W. Müller, S. Mitra, eds., Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems, Amsterdam, Netherlands, 2015.
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2014 | Conference Paper | LibreCat-ID: 25145
Virtual Platforms for Model-Based Design of Dependable Cyber-Physical System Software
M. Becker, C. Kuznik, W. Müller, in: 17th Euromicro Conference on Digital Systems Design (DSD), 2014.
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2014 | Conference Paper | LibreCat-ID: 25155
Fault Effect Modeling in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems
M. Becker, C. Kuznik, W. Müller, in: ACM/IEEE 5th International Conference on Cyber-Physical Systems, 2014.
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2014 | Conference Paper | LibreCat-ID: 25161
Portierung der TriCore-Architektur auf QEMU
B. Koppelmann, M. Becker, W. Müller, in: 17. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2014) , 2014.
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2014 | Conference Paper | LibreCat-ID: 24305
Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation
F. Mischkalla, W. Müller, in: Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), IEEE, Greece, 2014.
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2014 | Journal Article | LibreCat-ID: 24302
Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU
B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, C. Scheytt, Design and Verification Conference (DVCON EUROPE) (2014).
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2014 | Journal Article | LibreCat-ID: 24309
Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure
C. Kuznik, W. Müller, Design, Automation and Test in Europe DATE, University Booth, Dresden (2014).
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2014 | Conference Paper | LibreCat-ID: 24311
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges
J.-H. Oetjens, M. Becker, C. Kuznik, W. Müller, N. Bannow, O. Brinkmann, A. Burger, M. Chaari, S. Chakraborty, R. Drechsler, W. Ecker, K. Grüttner, T. Kruse, H.M. Le, M. Mauderer, D. Mueller-Gritschneider, F. Poppen, H. Post, Se. Reiter, W. Rosenstiel, S. Roth, U. Schlichtmann, A. Von Schwerin, B.A. Tabacaru, A. Viehl, in: Design Automation Conference (DAC), 2014.
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2014 | Conference Paper | LibreCat-ID: 25120
Architectural Low-Power Design Using Transaction-Based System Simulation
F. Mischkalla, W. Müller, in: Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), IEEE, 2014.
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2014 | Conference Paper | LibreCat-ID: 25146
Source code annotated memory leak detection for soft real time embedded systems with resource constraints
M. tech. M.M. Joy, W. Müller, F.-J. Rammig, in: 12th IEEE International Conference on Embedded Computing, 2014.
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2014 | Conference Paper | LibreCat-ID: 25144
Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation
F. Mischkalla, W. Müller, in: PATMOS 2014, Palma de Mallorca, Spain, 2014.
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2014 | Conference Paper | LibreCat-ID: 36918
Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems
M. Becker, C. Kuznik, W. Müller, in: IEEE, Berlin, 2014.
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2014 | Conference Paper | LibreCat-ID: 36917
An Assisted Single Source Verification Metric Model Code Generation Methodology
C. Kuznik, W. Müller, G.B. Defo, in: San Francisco, USA, 2014.
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2014 | Conference Paper | LibreCat-ID: 25166
Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM
C. Kuznik, W. Müller, in: 26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, 2014.
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2014 | Conference Paper | LibreCat-ID: 25163
Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung
C. Kuznik, B.G. Defo, W. Müller, in: 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) , 2014.
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2014 | Journal Article | LibreCat-ID: 25151
An Assisted Single Source Verification Metric Model Code Generation Methodology
C. Kuznik, B.G. Defo, W. Müller, Electronic System Level Synthesis Conference (ESLSyn) (2014).
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2014 | Conference Paper | LibreCat-ID: 34585
Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU
B. Koppelmann, B. Messidat, M. Becker, W. Müller, J.C. Scheytt, in: Proceedings of the Design and Verification Conference Europe (DVCON Europe), München, 2014.
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2014 | Journal Article | LibreCat-ID: 25164
HeroeS - A Framework for Heterogeneous Software-Intensive System Design with SystemC
M. Becker, W. Müller, J. Stroop, U. Kiffmeier, Design, Automation and Test in Europe DATE, University Booth, Dresden (2014).
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2013 | Conference Paper | LibreCat-ID: 25270
Early Phase Memory Leak Detection in Embedded Software Designs with Virtual Memory Management Model
M. tech. M.M. Joy, W. Müller, F.-J. Rammig, in: Proceedings of AVICPS 2013, Dez. 2013 IEEE Computer Society, Linköping University Electronic Press, 2013.
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2013 | Conference Paper | LibreCat-ID: 25271
AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS
D. He, W. Müller, in: Proceedings of International Conference on Applied Computing (AC), 2013.
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2013 | Conference Paper | LibreCat-ID: 25284
Efficient Power Intent Validation Using Loosely-Timed Simulation Models
F. Mischkalla, W. Müller, in: 23rd International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep. 2013, 2013.
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2013 | Conference Paper | LibreCat-ID: 25291
HeroeS: Virtual Platform Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time Architectures
M. Becker, U. Kiffmeier, W. Müller, in: 16th IEEE Computer Society Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2013.
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2013 | Conference Paper | LibreCat-ID: 25606
SystemC Verification Components - An enhanced OVM/UVM for SystemC
C. Kuznik, M. F. S. Oliveira, W. Müller, in: EdaWorkshop 13, 2013.
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2013 | Conference Paper | LibreCat-ID: 25612
Funktionale Verifikation von Low-Power Designs unter Verwendung Virtueller Prototypen
F. Mischkalla, W. Müller, in: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013.
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