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427 Publications
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2009 | Conference Paper | LibreCat-ID: 13636
E. Lübbers and M. Platzner, “Cooperative Multithreading in Dynamically Reconfigurable Systems,” in Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , 2009.
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2009 | Conference Paper | LibreCat-ID: 13637
H. Giefers and M. Platzner, “Program-driven Fine-grained Power Management for the Reconfigurable Mesh,” in Proceedings of the 19th International Workshop on Field Programmable Logic and Applications (FPL) , 2009.
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2009 | Conference Paper | LibreCat-ID: 13639
S. Drzevitzky, U. Kastens, and M. Platzner, “Proof-carrying Hardware: Towards Runtime Verification of Reconfigurable Modules,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2009.
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2009 | Conference Paper | LibreCat-ID: 2350
T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2009, pp. 275–278, doi: 10.1109/FCCM.2009.25.
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2009 | Conference Paper | LibreCat-ID: 2262
P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2009, pp. 11–18.
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2009 | Conference Paper | LibreCat-ID: 2238
T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000,” in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2009, pp. 119–124, doi: 10.1109/ReConFig.2009.32.
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2009 | Conference Paper | LibreCat-ID: 2261
T. Schumacher, C. Plessl, and M. Platzner, “An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2009, pp. 338–344.
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2009 | Conference Paper | LibreCat-ID: 2263
M. Grad and C. Plessl, “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2009, pp. 319–322.
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2008 | Conference Paper | LibreCat-ID: 2365
M. Platzner et al., “The GOmputer: Accelerating GO with FPGAs,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008, pp. 245–251.
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2008 | Bachelorsthesis | LibreCat-ID: 10628
A. Boschmann, Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen. Paderborn University, 2008.
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2008 | Bachelorsthesis | LibreCat-ID: 10641
D. Breitlauch, Selbstoptimierender Cache-Kontroller. Paderborn University, 2008.
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2008 | Bachelorsthesis | LibreCat-ID: 10644
T. Ceylan and C. Yalcin, Verteilte Simulation von mobilen Robotern mit EyeSim. Paderborn University, 2008.
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2008 | Conference Paper | LibreCat-ID: 10653
K. Glette, T. Gruber, P. Kaufmann, J. Torresen, B. Sick, and M. Platzner, “Comparing Evolvable Hardware to Conventional Classifiers for Electromyographic Prosthetic Hand Control,” in IEEE Adaptive Hardware and Systems (AHS), 2008, pp. 32–39.
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2008 | Conference Paper | LibreCat-ID: 10656
K. Glette, J. Torresen, P. Kaufmann, and M. Platzner, “A Comparison of Evolvable Hardware Architectures for Classification Tasks,” in IEEE Intl. Conf. on Evolvable Systems (ICES), 2008, vol. 5216, pp. 22–33.
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2008 | Mastersthesis | LibreCat-ID: 10669
M. Happe, Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern. Paderborn University, 2008.
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2008 | Preprint | LibreCat-ID: 10690
J. Torresen, K. Glette, M. Platzner, and P. Kaufmann, “Evolvable Hardware - Tutorial at Architecture of Computing Systems (ARCS).” 2008.
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2008 | Conference Paper | LibreCat-ID: 10691
P. Kaufmann and M. Platzner, “Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming,” in Genetic and Evolutionary Computation (GECCO), 2008, pp. 1219–1226.
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2008 | Bachelorsthesis | LibreCat-ID: 10696
T. Knieper, Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf. Paderborn University, 2008.
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2008 | Conference Paper | LibreCat-ID: 10698
T. Knieper, B. Defo, P. Kaufmann, and M. Platzner, “On Robust Evolution of Digital Hardware,” in Biologically Inspired Collaborative Computing (BICC), 2008, vol. 268, pp. 2313–222.
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2008 | Bachelorsthesis | LibreCat-ID: 10718
J. Niklas, Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme. Paderborn University, 2008.
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2008 | Bachelorsthesis | LibreCat-ID: 10721
M. Östermann, Raytracing on a Custom Instruction Set CPU. Paderborn University, 2008.
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2008 | Bachelorsthesis | LibreCat-ID: 10751
N. Westerheide, Design and Evaluation of MicroBlaze Multi-core Architectures. Paderborn University, 2008.
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2008 | Conference Paper | LibreCat-ID: 10778
H. Ghasemzadeh Mohammadi, H. Tabkhi, S. G. Miremadi, and A. Ejlali, “A cost-effective error detection and roll-back recovery technique for embedded microprocessor control logic,” in 2008 International Conference on Microelectronics, 2008, pp. 444–447.
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2008 | Conference Paper | LibreCat-ID: 13629
H. Giefers and M. Platzner, “Realizing Reconfigurable Mesh Algorithms on Softcore Arrays,” in Proceedings of the International Symposium on Systems, Architectures, Modeling and Simulation (SAMOS), 2008.
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2008 | Conference Paper | LibreCat-ID: 13630
E. Lübbers and M. Platzner, “Communication and Synchronization in Multithreaded Reconfigurable Computing Systems,” in Proceedings of the 8th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008.
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2008 | Conference Paper | LibreCat-ID: 2364
T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, and M. Platzner, “A Hardware Accelerator for k-th Nearest Neighbor Thinning,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008, pp. 245–251.
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2008 | Conference Paper | LibreCat-ID: 2372
T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers,” 2008.
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2007 | Mastersthesis | LibreCat-ID: 10623
T. Beisel, Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen. Paderborn University, 2007.
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2007 | Bachelorsthesis | LibreCat-ID: 10643
T. Ceylan and C. Yalcin, Distributed Simulation of mobile Robots using EyeSim. Paderborn University, 2007.
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2007 | Mastersthesis | LibreCat-ID: 10647
B. Defo, A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization. Paderborn University, 2007.
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2007 | Mastersthesis | LibreCat-ID: 10648
S. Döhre, Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme. Paderborn University, 2007.
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2007 | Conference Paper | LibreCat-ID: 10689
P. Kaufmann and M. Platzner, “Toward Self-adaptive Embedded Systems: Multi-objective Hardware Evolution,” in Architecture of Computing Systems (ARCS), 2007, vol. 4415, pp. 199–208.
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2007 | Bachelorsthesis | LibreCat-ID: 10709
R. Meiche, VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen. Paderborn University, 2007.
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2007 | Mastersthesis | LibreCat-ID: 10728
W. Reisch, Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS. Paderborn University, 2007.
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2007 | Mastersthesis | LibreCat-ID: 10729
E. Rethmeier, Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem. Paderborn University, 2007.
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2007 | Conference Paper | LibreCat-ID: 10735
T. Schumacher, E. Lübbers, P. Kaufmann, and M. Platzner, “Accelerating the Cube Cut Problem with an FPGA-Augmented Compute Cluster,” in Proceedings of the ParaFPGA Symposium, International Conference on Parallel Computing: Architectures, Algorithms and Applications (PARCO), 2007, vol. 15, pp. 749–756.
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2006 | Conference Paper | LibreCat-ID: 10688
P. Kaufmann and M. Platzner, “Multi-objective Intrinsic Hardware Evolution,” in Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD), 2006.
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2006 | Bachelorsthesis | LibreCat-ID: 10716
R. Mühlenbernd, FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks. Paderborn University, 2006.
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2006 | Conference Paper | LibreCat-ID: 13624
K. Danne, R. Mühlenbernd, and M. Platzner, “Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions,” in Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL), 2006.
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2006 | Conference Paper | LibreCat-ID: 13625
K. Danne and M. Platzner, “An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices,” in In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 2006.
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2006 | Conference Paper | LibreCat-ID: 13626
K. Danne and M. Platzner, “Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware,” in Proceedings of the 13th Reconfigurable Architectures Workshop (RAW), 2006.
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2005 | Conference Paper | LibreCat-ID: 13622
K. Danne and M. Platzner, “Memory-demanding Periodic Real-time Applications on FPGA Computers,” in Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-time Systems (ECRTS), 2005.
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2004 | Conference Paper | LibreCat-ID: 2415
C. Plessl and M. Platzner, “Virtualization of Hardware – Introduction and Survey,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2004, pp. 63–69.
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2004 | Conference Paper | LibreCat-ID: 13619
H. Walder, S. Nobs, and M. Platzner, “XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems,” in Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2004.
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2003 | Conference Paper | LibreCat-ID: 2422
R. Enzler, C. Plessl, and M. Platzner, “Co-simulation of a Hybrid Multi-Context Architecture,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2003, pp. 174–180.
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2003 | Conference Paper | LibreCat-ID: 13614
H. Walder and M. Platzner, “Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations,” in Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2003, pp. 284–287.
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2003 | Conference Paper | LibreCat-ID: 13615
C. Steiger, H. Walder, and M. Platzner, “Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices,” in Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL), 2003, pp. 575–584.
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2002 | Conference Paper | LibreCat-ID: 13611
H. Walder and M. Platzner, “Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform,” in Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2002, pp. 24–30.
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2001 | Conference Paper | LibreCat-ID: 2428
C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2001, pp. 85–91.
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2001 | Conference Paper | LibreCat-ID: 2432
R. Enzler, M. Platzner, C. Plessl, L. Thiele, and G. Tröster, “Reconfigurable Processors for Handhelds and Wearables: Application Analysis,” in Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 2001, vol. 4525, pp. 135–146.
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2001 | Misc | LibreCat-ID: 13463
R. Enzler and M. Platzner, Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1), 2001.
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2000 | Conference Paper | LibreCat-ID: 13609
M. H. Eisenring and M. Platzner, “An Implementation Framework for Run-time Reconfigurable Systems,” in Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE), 2000, pp. 151–157.
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2000 | Conference Paper | LibreCat-ID: 13610
M. Eisenring and M. Platzner, “Optimization of Run-time Reconfigurable Embedded Systems,” in Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL), 2000, pp. 565–574.
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1998 | Journal Article | LibreCat-ID: 10607
M. Platzner, “Reconfigurable Computer Architectures,” e&i Elektrotechnik und Informationstechnik, vol. 115, pp. 143–148, 1998.
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1998 | Journal Article | LibreCat-ID: 10608
M. Platzner and B. Rinner, “Design and Implementation of a Parallel Constraint Satisfaction Algorithm,” International Journal of Computers & Their Applications, vol. 5, pp. 106–116, 1998.
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1998 | Misc | LibreCat-ID: 13464
M. Platzner, B. Rinner, and R. Weiss, A Distributed Computer Architecture for Fast Qualitative Simulation . Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities, 1998, pp. 106–107.
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1997 | Journal Article | LibreCat-ID: 10609
M. Platzner, B. Rinner, and R. Weiss, “A Computer Architecture to Support Qualitative Simulation in Industrial Applications,” e & i Elektrotechnik und Informationstechnik, vol. 114, pp. 13–18, 1997.
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1997 | Conference Paper | LibreCat-ID: 13603
M. Platzner and L. Peters, “Fast Signature Segmentation on a Multi-DSP Architecture,” in Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing, 1997, vol. 3166.
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1997 | Conference Paper | LibreCat-ID: 13604
T. Röwekamp, M. Platzner, and L. Peters, “Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP,” in Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT), 1997, pp. 829–833.
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1996 | Conference Paper | LibreCat-ID: 13602
E. Lind, M. Platzner, and B. Rinner, “A Multi-DSP System with Dynamically Reconfigurable Processors,” in Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT), 1996.
LibreCat
1995 | Journal Article | LibreCat-ID: 10610
M. Platzner, B. Rinner, and R. Weiss, “Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation,” J.UCS Journal of Universal Computer Science, vol. 12, pp. 811–820, 1995.
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1995 | Conference Paper | LibreCat-ID: 13469
M. Platzner, B. Rinner, and R. Weiss, “A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs,” in Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing , 1995, pp. 311–318.
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1995 | Conference Paper | LibreCat-ID: 13470
E. Brenner et al., “High-Performance Simulators Based on Multi-TMS320C40,” in Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference, 1995.
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1995 | Conference Paper | LibreCat-ID: 13471
G. Friedl, M. Platzner, and B. Rinner, “A Special-Purpose Coprocessor for Qualitative Simulation,” in Proceedings of the EURO-PAR’95 International Conference on Parallel Processing, 1995, pp. 695–698.
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1995 | Conference Paper | LibreCat-ID: 13472
M. Platzner, B. Rinner, and R. Weiss, “Parallel Qualitative Simulation,” in Proceedings of the EUROSIM Congress, 1995, pp. 231–236.
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