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427 Publications
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2024 | Journal Article | LibreCat-ID: 52686
Q. A. Ahmed, T. Wiersema, and M. Platzner, “Post-configuration Activation of Hardware Trojans in FPGAs,” Journal of Hardware and Systems Security, 2024, doi: 10.1007/s41635-024-00147-5.
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2023 | Preprint | LibreCat-ID: 43048
C. Lienen, S. H. Middeke, and M. Platzner, “fpgaDDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications.” 2023.
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2023 | Conference Paper | LibreCat-ID: 44194 | 
Q. A. Ahmed, M. Awais, and M. Platzner, “MAAS: Hiding Trojans in Approximate Circuits,” presented at the The 24th International Symposium on Quality Electronic Design (ISQED’23), San Fransico CA 94023-0607, USA, 2023.
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2023 | Bachelorsthesis | LibreCat-ID: 45762
F. Simon-Mertens, Effizienzanalyse leichtgewichtiger Neuronaler Netze für FPGA-basierte Modulationsklassifikation. 2023.
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2023 | Mastersthesis | LibreCat-ID: 45917
M. Raeisi Nafchi, Reconfigurable Random Forest Implementation on FPGA. Paderborn University, 2023.
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2023 | Mastersthesis | LibreCat-ID: 45916
N. Yadalam Murali Kumar, Data Analytics for Predictive Maintenance of Time Series Data. Paderborn University, 2023.
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2023 | Mastersthesis | LibreCat-ID: 46075
M. Raeisi Nafchi, Reconfigurable Random Forest Implementation on FPGA. 2023.
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2023 | Preprint | LibreCat-ID: 46229
C. Lienen, A. P. Nowosad, and M. Platzner, “Mapping and Optimizing Communication in ROS 2-based Applications on Configurable System-on-Chip Platforms.” .
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2023 | Conference Paper | LibreCat-ID: 45913
L. Clausing, Z. Guetattfi, P. Kaufmann, C. Lienen, and M. Platzner, “On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64,” 2023.
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2023 | Dissertation | LibreCat-ID: 47837
T. Hansmeier, XCS for Self-awareness in Autonomous Computing Systems. 2023.
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2023 | Bachelorsthesis | LibreCat-ID: 52480
A. Klassen, Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices. 2023.
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2023 | Conference Paper | LibreCat-ID: 53435
F. Jentzsch, “Hardware-Aware AutoML for Exploration of Custom FPGA Accelerators for RadioML,” 2023, doi: 10.1109/fpl60245.2023.00066.
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2022 | Conference Paper | LibreCat-ID: 29945
L. M. Witschen, T. Wiersema, L. D. Reuter, and M. Platzner, “Search Space Characterization for Approximate Logic Synthesis ,” presented at the 2022 59th ACM/IEEE Design Automation Conference (DAC), San Francisco, USA.
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2022 | Conference Paper | LibreCat-ID: 29865
L. M. Witschen, T. Wiersema, M. Artmann, and M. Platzner, “MUSCAT: MUS-based Circuit Approximation Technique,” presented at the Design, Automation and Test in Europe (DATE), Online.
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2022 | Conference Paper | LibreCat-ID: 30971
T. Hansmeier and M. Platzner, “Integrating Safety Guarantees into the Learning Classifier System XCS,” in Applications of Evolutionary Computation, EvoApplications 2022, Proceedings, Madrid, 2022, vol. 13224, pp. 386–401, doi: 10.1007/978-3-031-02462-7_25.
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2022 | Conference Paper | LibreCat-ID: 32855
L. Clausing and M. Platzner, “ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support,” in 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Lyon, France, 2022, pp. 120–127, doi: 10.1109/ipdpsw55747.2022.00029.
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2022 | Conference Paper | LibreCat-ID: 33253
T. Hansmeier, M. Brede, and M. Platzner, “XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion,” in GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Boston, MA, USA, 2022, pp. 2071–2079, doi: 10.1145/3520304.3533977.
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2022 | Dissertation | LibreCat-ID: 29769 |
Q. A. Ahmed, Hardware Trojans in Reconfigurable Computing. Paderborn: Paderborn University, Paderborn, Germany, 2022.
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2022 | Preprint | LibreCat-ID: 29541
C. Lienen and M. Platzner, “ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications.” 2022.
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2022 | Conference Paper | LibreCat-ID: 34007
C. Lienen and M. Platzner, “Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS,” presented at the 2022 Sixth IEEE International Conference on Robotic Computing (IRC) , Neaples, Italy.
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2022 | Conference Paper | LibreCat-ID: 34005
C. Lienen and M. Platzner, “Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications,” presented at the 25th Euromicro Conference on Digital System Design (DSD), Maspalomas, Gran Canaria, Spain, doi: 10.1109/DSD57027.2022.00088.
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2022 | Conference Paper | LibreCat-ID: 32342
Q. A. Ahmed and M. Platzner, “On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs,” presented at the IEEE Computer Society Annual Symposium on VLSI Aliathon Resort, Pafos, Cyprus, 2022.
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2022 | Bachelorsthesis | LibreCat-ID: 42839
F. Mehlich, An Evaluation of XCS on the OpenAI Gym. Paderborn: Paderborn University, 2022.
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2022 | Journal Article | LibreCat-ID: 33990
F. Jentzsch, Y. Umuroglu, A. Pappalardo, M. Blott, and M. Platzner, “RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures,” IEEE Micro, vol. 42, no. 6, pp. 125–133, 2022, doi: 10.1109/MM.2022.3202091.
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2022 | Mastersthesis | LibreCat-ID: 45715
V. I. Tcheussi Ngayap, FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators. 2022.
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2022 | Mastersthesis | LibreCat-ID: 45914
S. Manjunatha, Dealing With Pre-Processing And Feature Extraction Of Time-Series Data In Predictive Maintenance. Paderborn University , 2022.
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2022 | Mastersthesis | LibreCat-ID: 45915
P. Kaur , Analysis of Time-Series Classification in Conditional Monitoring Systems. Paderborn University , 2022.
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2021 | Dissertation | LibreCat-ID: 26746 |
T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware. Paderborn: Paderborn University, 2021.
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2021 | Journal Article | LibreCat-ID: 29150
C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics Systems with ReconROS,” ACM Transactions on Reconfigurable Technology and Systems, pp. 1–20, 2021, doi: 10.1145/3494571.
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2021 | Mastersthesis | LibreCat-ID: 29151
C. Kashikar, A Comparison of Machine Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes. Paderborn: Paderborn University, 2021.
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2021 | Conference Paper | LibreCat-ID: 21610
M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis,” in Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, Virtual, 2021, pp. 27–32.
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2021 | Bachelorsthesis | LibreCat-ID: 22216
J. W. Rehnen, Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib. 2021.
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2021 | Conference Paper | LibreCat-ID: 22309
M. Awais and M. Platzner, “MCTS-Based Synthesis Towards Efficient Approximate Accelerators,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI, Tampa, Florida USA (Virtual), 2021, pp. 384–389.
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2021 | Bachelorsthesis | LibreCat-ID: 22483
M. Brede, Implementation and Profiling of XCS in the Context of Embedded Systems. Paderborn: Paderborn University, 2021.
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2021 | Conference Paper | LibreCat-ID: 21953
L. M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, and M. Platzner, “Timing Optimization for Virtual FPGA Configurations,” in Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21), Virtual conference, doi: 10.1007/978-3-030-79025-7_4.
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2021 | Journal Article | LibreCat-ID: 30906
A. Boschmann, D. Neuhaus, S. Vogt, C. Kaltschmidt, M. Platzner, and S. Dosen, “Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis,” Journal of NeuroEngineering and Rehabilitation, vol. 18, no. 1, Art. no. 25, 2021, doi: 10.1186/s12984-021-00822-6.
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2021 | Journal Article | LibreCat-ID: 30907
A. Rodriguez, A. Otero, M. Platzner, and E. De la Torre, “Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs,” IEEE Transactions on Computers, pp. 1–1, 2021, doi: 10.1109/tc.2021.3107196.
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2021 | Conference Paper | LibreCat-ID: 29137
T. Hansmeier, “Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS,” presented at the International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART ’21), Online, 2021, doi: 10.1145/3468044.3468055.
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2021 | Mastersthesis | LibreCat-ID: 29540
M. A. Sheikh, Design and Implementation of a ReconROS-based Obstacle Avoidance System. Paderborn University, 2021.
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2021 | Preprint | LibreCat-ID: 22764 |
C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics Systems with ReconROS,” arXiv:2107.07208. 2021.
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2021 | Conference Paper | LibreCat-ID: 21813
T. Hansmeier and M. Platzner, “An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS,” in GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Lille, France, 2021, pp. 1639–1647, doi: 10.1145/3449726.3463159.
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2021 | Journal Article | LibreCat-ID: 27841
M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, and T. Wiersema, “Software/Hardware Co-Verification for Custom Instruction Set Processors,” IEEE Access, 2021, doi: 10.1109/ACCESS.2021.3131213.
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2021 | Conference Paper | LibreCat-ID: 29138
Q. A. Ahmed, “Hardware Trojans in Reconfigurable Computing,” 2021, doi: 10.1109/vlsi-soc53125.2021.9606974.
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2021 | Conference Paper | LibreCat-ID: 20681 |
Q. A. Ahmed, T. Wiersema, and M. Platzner, “Malicious Routing: Circumventing Bitstream-level Verification for FPGAs,” presented at the Design, Automation and Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France, 2021, doi: 10.23919/DATE51398.2021.9474026.
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2021 | Conference Paper | LibreCat-ID: 30909
L. Clausing, “ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip,” 2021, doi: 10.1145/3468044.3468056.
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2021 | Conference Paper | LibreCat-ID: 30908
H. Ghasemzadeh Mohammadi et al., “FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics,” 2021, doi: https://doi.org/10.1007/978-3-030-93736-2_27.
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2020 | Conference Paper | LibreCat-ID: 3583
Z. Guetttatfi, P. Kaufmann, and M. Platzner, “Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices,” in Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), 2020.
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2020 | Mastersthesis | LibreCat-ID: 21324
K. Chandrakar, Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis. 2020.
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2020 | Bachelorsthesis | LibreCat-ID: 21432
L.-S. Henke, Evaluation of a ReconOS-ROS Combination based on a Video Processing Application. 2020.
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2020 | Journal Article | LibreCat-ID: 17369
N. Ho, P. Kaufmann, and M. Platzner, “Evolution of Application-Specific Cache Mappings,” International Journal of Hybrid intelligent Systems, 2020.
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2020 | Preprint | LibreCat-ID: 20748
L. M. Witschen, T. Wiersema, and M. Platzner, “Search Space Characterization for AxC Synthesis,” Fifth Workshop on Approximate Computing (AxC 2020). .
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2020 | Conference Paper | LibreCat-ID: 20750
C. Lienen, M. Platzner, and B. Rinner, “ReconROS: Flexible Hardware Acceleration for ROS2 Applications,” in Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT), 2020.
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2020 | Bachelorsthesis | LibreCat-ID: 20820
S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays. 2020.
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2020 | Mastersthesis | LibreCat-ID: 20821
V. Jaganath, Extension and Evaluation of Python-based High-Level Synthesis Tool Flows. 2020.
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2020 | Conference Paper | LibreCat-ID: 17063
T. Hansmeier, P. Kaufmann, and M. Platzner, “An Adaption Mechanism for the Error Threshold of XCSF,” in GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Cancún, Mexico, 2020, pp. 1756–1764, doi: 10.1145/3377929.3398106.
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2020 | Journal Article | LibreCat-ID: 15836
K. Bellman et al., “Self-aware Cyber-Physical Systems,” ACM Transactions on Cyber-Physical Systems, vol. Accepted for Publication, pp. 1–24, 2020.
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2020 | Conference Paper | LibreCat-ID: 16363
T. Hansmeier, P. Kaufmann, and M. Platzner, “Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold,” in GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Cancún, Mexico, 2020, pp. 125–126.
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2020 | Conference Paper | LibreCat-ID: 20838
A. Lösch and M. Platzner, “MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes,” 2020, doi: 10.1109/ipdpsw50202.2020.00012.
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2020 | Mastersthesis | LibreCat-ID: 21433
F. P. Jentzsch, Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture. 2020.
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2019 | Preprint | LibreCat-ID: 16853
L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits,” Fourth Workshop on Approximate Computing (AxC 2019). .
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2019 | Conference Paper | LibreCat-ID: 10577
L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump Search: A Fast Technique for the Synthesis of Approximate Circuits,” in Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19, Tysons Corner, VA, USA, 2019.
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2019 | Conference Paper | LibreCat-ID: 15422
N. Ho, P. Kaufmann, and M. Platzner, “Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor,” in World Congress on Nature and Biologically Inspired Computing (NaBIC), 2019.
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2019 | Mastersthesis | LibreCat-ID: 15883
S. Kumar Jeyakumar, Incremental learning with Support Vector Machine on embedded platforms. 2019.
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2019 | Mastersthesis | LibreCat-ID: 15920
M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking. Universität Paderborn, 2019.
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2019 | Mastersthesis | LibreCat-ID: 14831
N. S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data Sets. Paderborn University, 2019.
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2019 | Mastersthesis | LibreCat-ID: 15946
J. Mehta, Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recongurable System-on-Chip. 2019.
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2019 | Mastersthesis | LibreCat-ID: 14546
T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.
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2019 | Conference Paper | LibreCat-ID: 31067
Z. Guettatfi, M. Platzner, O. Kermia, and A. Khouas, “An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware,” 2019, doi: 10.1109/ipdpsw.2019.00027.
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2019 | Conference Paper | LibreCat-ID: 9913 |
Q. A. Ahmed, T. Wiersema, and M. Platzner, “Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan,” in Applied Reconfigurable Computing, Darmstadt, Germany, 2019, vol. 11444, pp. 127–136, doi: 10.1007/978-3-030-17227-5_10.
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2019 | Mastersthesis | LibreCat-ID: 15874 |
C. Lienen, Implementing a Real-time System on a Platform FPGA operated with ReconOS. Universität Paderborn.
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2019 | Journal Article | LibreCat-ID: 12871 |
M. Platzner and C. Plessl, “FPGAs im Rechenzentrum,” Informatik Spektrum, 2019, doi: 10.1007/s00287-019-01187-w.
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2019 | Mastersthesis | LibreCat-ID: 52478
J. D. Mehta, Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip. 2019.
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2018 | Conference Paper | LibreCat-ID: 3362
A. Lösch, A. Wiens, and M. Platzner, “Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes,” in Proceedings of the International Conference on Architecture of Computing Systems (ARCS), 2018, vol. 10793, pp. 73–84.
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2018 | Bachelorsthesis | LibreCat-ID: 3365
J.-P. Schnuer, Static Scheduling Algorithms for Heterogeneous Compute Nodes. Universität Paderborn, 2018.
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2018 | Bachelorsthesis | LibreCat-ID: 3366
M. Croce, Evaluation of OpenCL-based Compilation for FPGAs. Universität Paderborn, 2018.
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2018 | Conference Paper | LibreCat-ID: 3373
T. Hansmeier, M. Platzner, and D. Andrews, “An FPGA/HMC-Based Accelerator for Resolution Proof Checking,” in ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications, Santorini, Greece, 2018, vol. 10824, pp. 153–165.
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2018 | Preprint | LibreCat-ID: 3586
L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner, “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,” Third Workshop on Approximate Computing (AxC 2018). .
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2018 | Preprint | LibreCat-ID: 1165
L. M. Witschen, T. Wiersema, and M. Platzner, “Making the Case for Proof-carrying Approximate Circuits,” 4th Workshop On Approximate Computing (WAPCO 2018). 2018.
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2018 | Conference Paper | LibreCat-ID: 5547
A. Lösch and M. Platzner, “A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes,” in 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Milan, Italy, 2018.
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2018 | Mastersthesis | LibreCat-ID: 10782
L. Clausing, Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data. Ruhr-University Bochum, 2018.
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2018 | Bachelorsthesis | LibreCat-ID: 1097
F. P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable Security Monitors. Universität Paderborn, 2018.
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2017 | Bachelorsthesis | LibreCat-ID: 3580
T. Hansmeier, An FPGA Accelerator for Checking Resolution Proofs. Universität Paderborn, 2017.
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2017 | Mastersthesis | LibreCat-ID: 1157
L. M. Witschen, A Framework for the Synthesis of Approximate Circuits. Universität Paderborn, 2017.
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2017 | Mastersthesis | LibreCat-ID: 74
C. Knorr, OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten. Universität Paderborn, 2017.
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2017 | Conference Paper | LibreCat-ID: 65
A. Lösch and M. Platzner, “reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements,” in Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2017.
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2017 | Journal Article | LibreCat-ID: 68
T. Isenberg, M. Platzner, H. Wehrheim, and T. Wiersema, “Proof-Carrying Hardware via Inductive Invariants,” ACM Transactions on Design Automation of Electronic Systems, no. 4, pp. 61:1--61:23, 2017.
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