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165 Publications
1998 | Misc | LibreCat-ID: 13091
N. Yarmolik, Vyacheslav, Sybille Hellebrand, and Hans-Joachim Wunderlich. Efficient Consistency Checking for Embedded Memories. 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1998.
LibreCat
1998 | Misc | LibreCat-ID: 13092
N. Yarmolik, Vyacheslav, Sybille Hellebrand, and Hans-Joachim Wunderlich. Efficient Consistency Checking for Embedded Memories. 10th GI/ITG/GMM/IEEE Workshop, 1998.
LibreCat
1998 | Book Chapter | LibreCat-ID: 13060
Hellebrand, Sybille, Hans-Joachim Wunderlich, and Andre Hertwig. “Mixed-Mode BIST Using Embedded Processors.” In Mixed-Mode BIST Using Embedded Processors. 5. In: M. Nicolaidis, Y. Zorian, D. K. Pradhan (Eds.): On-Line Testing for VLSI, Boston: Kluwer Academic Publishers 1998: Kluwer Academic Publishers, 1998.
LibreCat
1998 | Journal Article | LibreCat-ID: 13061
Hellebrand, Sybille, Hans-Joachim Wunderlich, and Andre Hertwig. “Mixed-Mode BIST Using Embedded Processors.” Journal of Electronic Testing Theory and Applications - JETTA 12, no. 1/2 (1998): 127–38.
LibreCat
1998 | Journal Article | LibreCat-ID: 13064
Hellebrand, Sybille, Andre Hertwig, and Hans-Joachim Wunderlich. “Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications.” IEEE Design and Test 15, no. 4 (1998): 36–41.
LibreCat
1998 | Conference Paper | LibreCat-ID: 13007
Hertwig, Andre, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Fast Self-Recovering Controllers.” In 16th IEEE VLSI Test Symposium (VTS’98), 296–302. Monterey, CA, USA: IEEE, 1998. https://doi.org/10.1109/vtest.1998.670883.
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1998 | Conference Paper | LibreCat-ID: 13008
Hellebrand, Sybille, Hans-Joachim Wunderlich, and Vyacheslav N. Yarmolik. “Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs.” In Design Automation and Test in Europe (DATE’98), 173–79. Paris, France, 1998. https://doi.org/10.1109/date.1998.655853.
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1998 | Conference Paper | LibreCat-ID: 13063
N. Yarmolik, Vyacheslav, Yuri V. Klimets, Sybille Hellebrand, and Hans-Joachim Wunderlich. “New Transparent RAM BIST Based on Self-Adjusting Output Data Compression.” In Design & Diagnostics of Electronic Circuits & Systems (DDECS’98), 27–33. Szczyrk, Poland, 1998.
LibreCat
1997 | Misc | LibreCat-ID: 13089
Tsai, Kun-Han, Sybille Hellebrand, Janusz Rajski, and Malgorzata Marek-Sadowska. STARBIST: Scan Autocorrelated Random Pattern Generation. 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1997.
LibreCat
1997 | Misc | LibreCat-ID: 13090
Hertwig, Andre, Sybille Hellebrand, and Hans-Joachim Wunderlich. Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. 3rd IEEE International On-Line Testing Workshop, Crete, Greece, 1997.
LibreCat
1997 | Conference Paper | LibreCat-ID: 13009
Tsai, Kun-Han, Sybille Hellebrand, Malgorzata Marek-Sadowska, and Janusz Rajski. “STARBIST: Scan Autocorrelated Random Pattern Generation.” In 34th ACM/IEEE Design Automation Conference (DAC’97). Anaheim, CA, USA: IEEE, 1997. https://doi.org/10.1109/dac.1997.597194.
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1996 | Misc | LibreCat-ID: 13087
Hellebrand, Sybille, and Hans-Joachim Wunderlich. Using Embedded Processors for BIST. 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1996.
LibreCat
1996 | Misc | LibreCat-ID: 13088
Hellebrand, Sybille, Hans-Joachim Wunderlich, and Andre Hertwig. Mixed-Mode BIST Using Embedded Processors. 2nd IEEE International On-Line Testing Workshop. Biarritz, France, 1996.
LibreCat
1996 | Conference Paper | LibreCat-ID: 13010
Hellebrand, Sybille, Hans-Joachim Wunderlich, and Andre Hertwig. “Mixed-Mode BIST Using Embedded Processors.” In IEEE International Test Conference (ITC’96), 195–204. Washington, DC, USA: IEEE, 1996. https://doi.org/10.1109/test.1996.556962.
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1995 | Report | LibreCat-ID: 13026
Hellebrand, Sybille, and Hans-Joachim Wunderlich. Synthesis Procedures for Self-Testable Controllers. University of Siegen, Germany, 1995.
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1995 | Report | LibreCat-ID: 13027
Hellebrand, Sybille, Hans-Joachim Wunderlich, F. Goncalves, and Joao Paulo Teixeira. Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. University Siegen, Germany, 1995.
LibreCat
1995 | Report | LibreCat-ID: 13028
Hellebrand, Sybille, Maik Herzog, and Hans-Joachim Wunderlich. Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. University of Siegen, Germany, 1995.
LibreCat
1995 | Misc | LibreCat-ID: 13086
Hellebrand, Sybille, Birgit Reeb, Steffen Tarnick, and Hans-Joachim Wunderlich. Pattern Generation for a Deterministic BIST Scheme. 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1995.
LibreCat
1995 | Journal Article | LibreCat-ID: 13011
Hellebrand, Sybille, Janusz Rajski, Steffen Tarnick, Srikanth Venkataraman, and B. Courtois. “Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers.” IEEE Transactions on Computers 44, no. 2 (1995): 223–33. https://doi.org/10.1109/12.364534.
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1995 | Conference Paper | LibreCat-ID: 13012
Hellebrand, Sybille, Birgit Reeb, Steffen Tarnick, and Hans-Joachim Wunderlich. “Pattern Generation for a Deterministic BIST Scheme.” In ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), 88–94. San Jose, CA, USA: IEEE, 1995. https://doi.org/10.1109/iccad.1995.479997.
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