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459 Publications
2025 | Preprint | LibreCat-ID: 61152
SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators
Y. Umuroglu, C. Berganski, F. Jentzsch, M. Danilowicz, T. Kryjak, C. Bezaitis, M. Sjalander, I. Colbert, T. Preusser, J. Petri-Koenig, M. Blott, (n.d.).
LibreCat
Y. Umuroglu, C. Berganski, F. Jentzsch, M. Danilowicz, T. Kryjak, C. Bezaitis, M. Sjalander, I. Colbert, T. Preusser, J. Petri-Koenig, M. Blott, (n.d.).
2025 | Journal Article | LibreCat-ID: 62020
Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators
M. Awais, H.G. Mohammadi, M. Platzner, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 33 (2025) 2395–2405.
LibreCat
| DOI
M. Awais, H.G. Mohammadi, M. Platzner, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 33 (2025) 2395–2405.
2025 | Conference Paper | LibreCat-ID: 62019
A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation
A.H. Hadipour, A. Jafari, M. Awais, M. Platzner, in: 2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), IEEE, 2025.
LibreCat
| DOI
A.H. Hadipour, A. Jafari, M. Awais, M. Platzner, in: 2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), IEEE, 2025.
2025 | Mastersthesis | LibreCat-ID: 62268
Design and Integration of Intra-Process Communication for ROS 2 into ReconROS
P. Bengaluru Amarnath, Design and Integration of Intra-Process Communication for ROS 2 into ReconROS, Paderborn University, 2025.
LibreCat
P. Bengaluru Amarnath, Design and Integration of Intra-Process Communication for ROS 2 into ReconROS, Paderborn University, 2025.
2025 | Conference Paper | LibreCat-ID: 64112
Deep&Wide: Achieving Area Efficiency in Scalable Approximate Accelerators
F. Jalil, M. Awais, Q.A. Ahmed, H.G. Mohammadi, T. Jungeblut, M. Platzner, in: 2025 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2025.
LibreCat
| DOI
F. Jalil, M. Awais, Q.A. Ahmed, H.G. Mohammadi, T. Jungeblut, M. Platzner, in: 2025 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2025.
2025 | Conference Paper | LibreCat-ID: 64113
A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation
A.H. Hadipour, A. Jafari, M. Awais, M. Platzner, in: 2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), IEEE, 2025.
LibreCat
| DOI
A.H. Hadipour, A. Jafari, M. Awais, M. Platzner, in: 2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), IEEE, 2025.
2024 | Journal Article | LibreCat-ID: 52686
Post-configuration Activation of Hardware Trojans in FPGAs
Q.A. Ahmed, T. Wiersema, M. Platzner, Journal of Hardware and Systems Security (2024).
LibreCat
| DOI
Q.A. Ahmed, T. Wiersema, M. Platzner, Journal of Hardware and Systems Security (2024).
2024 | Mastersthesis | LibreCat-ID: 54245
Exploring Custom FPGA Accelerators for DNN-based RF Fingerprinting
L.-S. Henke, Exploring Custom FPGA Accelerators for DNN-Based RF Fingerprinting, 2024.
LibreCat
L.-S. Henke, Exploring Custom FPGA Accelerators for DNN-Based RF Fingerprinting, 2024.
2024 | Conference Paper | LibreCat-ID: 54468
DeepApprox: Rapid Deep Learning based Design Space Exploration of Approximate Circuits via Check-pointing
M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: To Apear in IEEE ISVLSI 2024, 2024.
LibreCat
M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: To Apear in IEEE ISVLSI 2024, 2024.
2024 | Conference Paper | LibreCat-ID: 56481
FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers
C. Berganski, F. Jentzsch, M. Platzner, M. Kuhmichel, H. Giefers, in: 2024.
LibreCat
C. Berganski, F. Jentzsch, M. Platzner, M. Kuhmichel, H. Giefers, in: 2024.