Please note that LibreCat no longer supports Internet Explorer versions 8 or 9 (or earlier).
We recommend upgrading to the latest Internet Explorer, Google Chrome, or Firefox.
461 Publications
2026 | Journal Article | LibreCat-ID: 61152
Y. Umuroglu et al., “SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators,” ACM Transactions on Reconfigurable Technology and Systems, doi: 10.1145/3807510.
LibreCat
| DOI
2026 | Conference Paper | LibreCat-ID: 65501
L. Stasytis, F. Jentzsch, T. Preusser, Y. Umuroglu, J. Petri-Koenig, and Z. István, “Heuristic & Expert-Guided Buffer Sizing for Neural Network Inference Applications on FPGAs,” 2026, doi: 10.1109/icfpt67023.2025.00032.
LibreCat
| DOI
2026 | Conference Paper | LibreCat-ID: 65500
F. Jentzsch and M. Platzner, “Empirical QoR Estimation Flow for Fast Design Space Exploration of DNN Dataflow Accelerators,” 2026, doi: 10.1109/icfpt67023.2025.00044.
LibreCat
| DOI
2025 | Conference Paper | LibreCat-ID: 64112
F. Jalil, M. Awais, Q. A. Ahmed, H. G. Mohammadi, T. Jungeblut, and M. Platzner, “Deep&Wide: Achieving Area Efficiency in Scalable Approximate Accelerators,” 2025, doi: 10.1109/dsn-w65791.2025.00048.
LibreCat
| DOI
2025 | Conference Paper | LibreCat-ID: 64113
A. H. Hadipour, A. Jafari, M. Awais, and M. Platzner, “A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation,” 2025, doi: 10.1109/ddecs63720.2025.11006769.
LibreCat
| DOI
2025 | Journal Article | LibreCat-ID: 62020
M. Awais, H. G. Mohammadi, and M. Platzner, “Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 33, no. 9, pp. 2395–2405, 2025, doi: 10.1109/tvlsi.2025.3559377.
LibreCat
| DOI
2025 | Conference Paper | LibreCat-ID: 62019
A. H. Hadipour, A. Jafari, M. Awais, and M. Platzner, “A Two-Stage Approximation Methodology for Efficient DNN Hardware Implementation,” 2025, doi: 10.1109/ddecs63720.2025.11006769.
LibreCat
| DOI
2025 | Mastersthesis | LibreCat-ID: 62268
P. Bengaluru Amarnath, Design and Integration of Intra-Process Communication for ROS 2 into ReconROS. Paderborn University, 2025.
LibreCat
2024 | Journal Article | LibreCat-ID: 52686
Q. A. Ahmed, T. Wiersema, and M. Platzner, “Post-configuration Activation of Hardware Trojans in FPGAs,” Journal of Hardware and Systems Security, 2024, doi: 10.1007/s41635-024-00147-5.
LibreCat
| DOI
2024 | Conference Paper | LibreCat-ID: 54468
M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “DeepApprox: Rapid Deep Learning based Design Space Exploration of Approximate Circuits via Check-pointing,” presented at the IEEE Computer Society Annual Symposium on VLSI, Knoxville, Tennessee, USA, 2024.
LibreCat
2024 | Bachelorsthesis | LibreCat-ID: 58132
M. Hartinger, Controlling I/O Devices from Hardware-Mapped ReconROS Nodes. Paderborn University, 2024.
LibreCat
2024 | Conference Paper | LibreCat-ID: 56481
C. Berganski, F. Jentzsch, M. Platzner, M. Kuhmichel, and H. Giefers, “FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers,” presented at the International Conference on Field Programmable Technology, Sydney, 2024.
LibreCat
2024 | Mastersthesis | LibreCat-ID: 54245
L.-S. Henke, Exploring Custom FPGA Accelerators for DNN-based RF Fingerprinting. 2024.
LibreCat
2023 | Dissertation | LibreCat-ID: 47837
T. Hansmeier, XCS for Self-awareness in Autonomous Computing Systems. 2023.
LibreCat
2023 | Conference Paper | LibreCat-ID: 53794
C. Lienen et al., “AutonomROS: A ReconROS-based Autonomous Driving Unit,” 2023, doi: 10.1109/irc59093.2023.00056.
LibreCat
| DOI
2023 | Conference Paper | LibreCat-ID: 45913
L. Clausing, Z. Guetattfi, P. Kaufmann, C. Lienen, and M. Platzner, “On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64,” 2023, doi: https://doi.org/10.1007/978-3-031-42921-7_17.
LibreCat
| DOI
2023 | Conference Paper | LibreCat-ID: 46229
C. Lienen, A. P. Nowosad, and M. Platzner, “Mapping and Optimizing Communication in ROS 2-based Applications on Configurable System-on-Chip Platforms,” doi: https://doi.org/10.1145/3637843.3637846.
LibreCat
| DOI
| Download (ext.)
2023 | Conference Paper | LibreCat-ID: 43048
C. Lienen, S. H. Middeke, and M. Platzner, “fpgaDDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications,” 2023, doi: 10.1109/IROS55552.2023.10341921.
LibreCat
| DOI
| Download (ext.)
2023 | Book Chapter | LibreCat-ID: 45888 | 
H. Wehrheim, M. Platzner, E. Bodden, P. Schubert, F. Pauck, and M.-C. Jakobs, “Verifying Software and Reconfigurable Hardware Services,” in On-The-Fly Computing -- Individualized IT-services in dynamic markets, vol. 412, C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, and H. Wehrheim, Eds. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023, pp. 125–144.
LibreCat
| Files available
| DOI
2023 | Book Chapter | LibreCat-ID: 45893 |
T. Hansmeier, T. Kenter, M. Meyer, H. Riebler, M. Platzner, and C. Plessl, “Compute Centers I: Heterogeneous Execution Environments,” in On-The-Fly Computing -- Individualized IT-services in dynamic markets, vol. 412, C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, and H. Wehrheim, Eds. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023, pp. 165–182.
LibreCat
| Files available
| DOI