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151 Publications


2005 | Misc | LibreCat-ID: 13102
Oehler, P., & Hellebrand, S. (2005). Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria.
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2005 | Conference Paper | LibreCat-ID: 12999
Ali, M., Welzl, M., Zwicknagl, M., & Hellebrand, S. (2005). Considerations for Fault-Tolerant Networks on Chips. IEEE International Conference on Microelectronics (ICM’05). https://doi.org/10.1109/icm.2005.1590063
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2005 | Conference Paper | LibreCat-ID: 13000
Oehler, P., & Hellebrand, S. (2005). Low Power Embedded DRAMs with High Quality Error Correcting Capabilities. 10th IEEE European Test Symposium (ETS’05), 148–153. https://doi.org/10.1109/ets.2005.28
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2005 | Conference Paper | LibreCat-ID: 12998
Ali, M., Welzl, M., & Hellebrand, S. (2005). A Dynamic Routing Mechanism for Network on Chip. 23rd IEEE NORCHIP Conference, 70–73. https://doi.org/10.1109/norchp.2005.1596991
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2004 | Misc | LibreCat-ID: 13099
Breu, R., Fahringer, T., Fensel, D., Hellebrand, S., Middeldorp, A., & Scherzer, O. (2004). Im Westen viel Neues - Informatik an der Universität Innsbruck. OCG Journal, pp. 28-29.
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2004 | Misc | LibreCat-ID: 13100
Hellebrand, S., Wuertenberger, A., & S. Tautermann, C. (2004). Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. 9th IEEE European Test Symposium, Ajaccio, Corsica, France.
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2004 | Conference Paper | LibreCat-ID: 13001
Wuertenberger, A., S. Tautermann, C., & Hellebrand, S. (2004). Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. IEEE International Test Conference (ITC’04), 926–935. https://doi.org/10.1109/test.2004.1387357
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2003 | Misc | LibreCat-ID: 13098
Breu, R., Hellebrand, S., & Welzl, M. (2003). Experiences from Teaching Software Development in a Java Environment. Handouts ACS/IEEE Workshop on Practice and Experience with Java in Education, Tunis, Tunisia.
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2003 | Conference Paper | LibreCat-ID: 13002
Wuertenberger, A., S. Tautermann, C., & Hellebrand, S. (2003). A Hybrid Coding Strategy for Optimized Test Data Compression. IEEE International Test Conference (ITC’03), 451–459. https://doi.org/10.1109/test.2003.1270870
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2002 | Misc | LibreCat-ID: 13097
Hellebrand, S., & Wuertenberger, A. (2002). Alternating Run-Length Coding: A Technique for Improved Test Data Compression. IEEE International Workshop on Test Resource Partitioning, Baltimore, MD, USA.
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2002 | Journal Article | LibreCat-ID: 13003
Hellebrand, S., Wunderlich, H.-J., A. Ivaniuk, A., V. Klimets, Y., & N. Yarmolik, V. (2002). Efficient Online and Offline Testing of Embedded DRAMs. IEEE Transactions on Computers, 51(7), 801–809. https://doi.org/10.1109/tc.2002.1017700
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2002 | Journal Article | LibreCat-ID: 13069
Hellebrand, S., Liang, H.-G., & Wunderlich, H.-J. (2002). Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. Journal of Electronic Testing - Theory and Applications (JETTA), 18(2), 157–168.
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2002 | Journal Article | LibreCat-ID: 13070
Liang, H., Hellebrand, S., & Wunderlich, H.-J. (2002). A Mixed-Mode BIST Scheme Based on Folding Compression. Journal on Computer Science and Technology, 17(2), 203–212.
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2001 | Misc | LibreCat-ID: 13096
Liang, H.-G., Hellebrand, S., & Wunderlich, H.-J. (2001). Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. IEEE European Test Workshop, Stockholm, Sweden.
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2001 | Conference Paper | LibreCat-ID: 13004
Liang, H.-G., Hellebrand, S., & Wunderlich, H.-J. (2001). Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. IEEE International Test Conference (ITC’01), 894–902. https://doi.org/10.1109/test.2001.966712
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2001 | Journal Article | LibreCat-ID: 13047
Liang, H.-G., Hellebrand, S., & Wunderlich, H.-J. (2001). Deterministic BIST Scheme Based on Reseeding of Folding Counters. Journal of Computer Research and Development, (Jisuanji Yanjiu Yu Fazhan), 38(8), 931.
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2001 | Journal Article | LibreCat-ID: 13068
Hellebrand, S., Liang, H.-G., & Wunderlich, H.-J. (2001). A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. Journal of Electronic Testing - Theory and Applications (JETTA), 17(3/4), 341–349.
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2000 | Misc | LibreCat-ID: 13094
Hellebrand, S., & Wunderlich, H.-J. (2000). Hardwarepraktikum im Diplomstudiengang Informatik. Handbuch Lehre, Berlin, Raabe Verlag.
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2000 | Misc | LibreCat-ID: 13095
Hellebrand, S., Liang, H.-G., & Wunderlich, H.-J. (2000). A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. IEEE European Test Workshop, Cascais, Portugal.
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2000 | Conference Paper | LibreCat-ID: 13005
Hellebrand, S., Liang, H.-G., & Wunderlich, H.-J. (2000). A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. IEEE International Test Conference (ITC’00), 778–784. https://doi.org/10.1109/test.2000.894274
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