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10 Publications
2021 | Journal Article | LibreCat-ID: 29210
Wu L, Scheytt JC. Analysis and Design of a Charge Sampler With 70-GHz 1-dB Bandwidth in 130-nm SiGe BiCMOS. IEEE Transactions on Circuits and Systems I: Regular Papers. 2021;68(9):3668-3681. doi:10.1109/tcsi.2021.3094428
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2021 | Dissertation | LibreCat-ID: 52664
Wu L. Ultrabreitbandige Sampler in SiGe-BiCMOS-Technologie Für Analog-Digital-Wandler Mit Zeitversetzter Abtastung. Vol 402.; 2021.
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2020 | Conference Paper | LibreCat-ID: 24021
Wu L, Weizel M, Scheytt C. Above 60 GHz Bandwidth 10 GS/s Sampling Rate Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE; 2020. doi:10.1109/ISCAS45731.2020.9180947
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2019 | Conference Paper | LibreCat-ID: 24049
Wu L, Weizel M, Scheytt C. 70 GHz Large-signal Bandwidth Sampler Using Current-mode Integrate-and-Hold Circuit in 130 nm SiGe BiCMOS Technology. In: Asia-Pacific Microwave Conference (APMC). ; 2019. doi:10.1109/APMC46564.2019.9038239
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2019 | Conference Paper | LibreCat-ID: 24052
Wu L, Weizel M, Scheytt C. A 70 GHz Small-signal Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology. In: 26th IEEE International Conference on Electronics Circuits and Systems (ICECS). ; 2019. doi:10.1109/ICECS46596.2019.8965046
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2018 | Conference Paper | LibreCat-ID: 24196
Wu L, Hussain MK, Abughannam S, Müller W, Scheytt C, Ecker W. Analog fault simulation automation at schematic level with random sampling techniques. In: 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)) . IEEE; 2018. doi:10.1109/DTIS.2018.8368549
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2018 | Patent | LibreCat-ID: 24198
Scheytt C, Wu L. Integrier‐ und Halte‐Schaltung . Published online 2018.
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2017 | Conference Paper | LibreCat-ID: 24223
Wu L, Abughannam S, Müller W, Scheytt C, Ecker W. SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study. In: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES). ; 2017:68.
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2016 | Conference Paper | LibreCat-ID: 24263
Abughannam S, Wu L, Müller W, Scheytt C, Ecker W, Novello C. Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study. In: Analog 2016 - VDE. ; 2016.
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2015 | Conference Paper | LibreCat-ID: 24289
Müller W, Wu L, Scheytt C, Becker M, Schoenberg S. On the Correlation of HW Faults and SW Errors. In: Mueller-Gritschneder D, Müller W, Mitra S, eds. Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014). ; 2015.
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