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367 Publications


2007 | Bachelorsthesis | LibreCat-ID: 10643
Ceylan T, Yalcin C. Distributed Simulation of Mobile Robots Using EyeSim. Paderborn University; 2007.
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2007 | Mastersthesis | LibreCat-ID: 10648
Döhre S. Entwurf Und Implementierung Einer RocketIO-Basierten Kommunikationsschnittstelle Für Multi-FPGA Systeme. Paderborn University; 2007.
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2007 | Conference Paper | LibreCat-ID: 13628
Lübbers E, Platzner M. ReconOS: An RTOS Supporting Hard-and Software Threads. In: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2007. doi:10.1109/fpl.2007.4380686
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2007 | Journal Article | LibreCat-ID: 10625
Bergmann N, Platzner M, Teich J. Dynamically Reconfigurable Architectures (editorial). {EURASIP} Journal on Embedded Systems. 2007;2007:1-2. doi:10.1155/2007/28405
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2006 | Bachelorsthesis | LibreCat-ID: 10716
Mühlenbernd R. FPGA-Implementierung Eines Server-Basierten Schedulers Für Periodische Hardwaretasks. Paderborn University; 2006.
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2006 | Conference Paper | LibreCat-ID: 13626
Danne K, Platzner M. Partitioned Scheduling of Periodic Real-time Tasks onto Reconfigurable Hardware. In: Proceedings of the 13th Reconfigurable Architectures Workshop (RAW). IEEE CS Press; 2006.
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2006 | Conference Paper | LibreCat-ID: 2401
Plessl C, Platzner M, Thiele L. Optimal Temporal Partitioning based on Slowdown and Retiming. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2006:345-348. doi:10.1109/FPT.2006.270344
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2006 | Conference Paper | LibreCat-ID: 13624
Danne K, Mühlenbernd R, Platzner M. Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions. In: Proceedings of the 16th International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2006.
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2006 | Conference Paper | LibreCat-ID: 10688
Kaufmann P, Platzner M. Multi-objective Intrinsic Hardware Evolution. In: Intl. Conf. Military Applications of Programmable Logic Devices (MAPLD). ; 2006.
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2006 | Conference Paper | LibreCat-ID: 13625
Danne K, Platzner M. An EDF Schedulability Test for Periodic Tasks on Reconfigurable Hardware Devices. In: In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). ; 2006.
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2005 | Conference Paper | LibreCat-ID: 13621
Danne K, Platzner M. Periodic real-time scheduling for FPGA computers. In: Proceedings of the Third International Workshop on Intelligent Solutions in Embedded Systems (WISES). ; 2005. doi:10.1109/wises.2005.1438720
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2005 | Journal Article | LibreCat-ID: 2412
Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable processors. Microprocessors and Microsystems. 2005;29(2-3):63-73. doi:10.1016/j.micpro.2004.06.004
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2005 | Conference Paper | LibreCat-ID: 13622
Danne K, Platzner M. Memory-demanding Periodic Real-time Applications on FPGA Computers. In: Work-in-Progress Proceedings of the 17th Euromicro Conference on Real-Time Systems (ECRTS). ; 2005.
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2005 | Conference Paper | LibreCat-ID: 13623
Danne K, Platzner M. A heuristic approach to schedule periodic real-time tasks on reconfigurable hardware. In: Proceedings of the 15th International Conference on Field Programmable Logic and Applications (FPL). IEEE CS Press; 2005. doi:10.1109/fpl.2005.1515787
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2005 | Conference Paper | LibreCat-ID: 2411
Plessl C, Platzner M. Zippy – A coarse-grained reconfigurable array with support for hardware virtualization. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2005:213-218. doi:10.1109/ASAP.2005.69
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2004 | Journal Article | LibreCat-ID: 10742
Steiger C, Walder H, Platzner M. Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks. {IEEE} Transactions on Computers. 2004;53(11):1393-1407. doi:10.1109/tc.2004.99
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2004 | Conference Paper | LibreCat-ID: 13619
Walder H, Nobs S, Platzner M. XF-BOARD: A Prototyping Platform for Reconfigurable Hardware Operating Systems. In: Proceedings of the 4th International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2004.
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2004 | Conference Paper | LibreCat-ID: 2415
Plessl C, Platzner M. Virtualization of Hardware – Introduction and Survey. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2004:63-69.
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2004 | Conference Paper | LibreCat-ID: 13618
Walder H, Platzner M. A Runtime Environment for Reconfigurable Hardware Operating Systems. In: Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL). Berlin, Heidelberg: Springer; 2004:831-835. doi:10.1007/978-3-540-30117-2_84
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2004 | Conference Paper | LibreCat-ID: 13620
Dyer M, Platzner M, Thiele L. Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine. In: Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE CS Press; 2004. doi:10.1109/fccm.2004.31
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2003 | Conference Paper | LibreCat-ID: 13614
Walder H, Platzner M. Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In: Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2003:284-287.
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2003 | Conference Paper | LibreCat-ID: 13615
Steiger C, Walder H, Platzner M. Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices. In: Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL). Berlin, Heidelberg: Springer; 2003:575-584. doi:10.1007/978-3-540-45234-8_56
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2003 | Conference Paper | LibreCat-ID: 2418
Plessl C, Platzner M. TKDM – A Reconfigurable Co-processor in a PC’s Memory Slot. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2003:252-259. doi:10.1109/FPT.2003.1275755
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2003 | Journal Article | LibreCat-ID: 2420
Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. Journal of Supercomputing. 2003;26(2):109-129. doi:10.1023/a:1024443416592
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2003 | Journal Article | LibreCat-ID: 2419
Plessl C, Enzler R, Walder H, et al. The Case for Reconfigurable Hardware in Wearable Computing. Personal and Ubiquitous Computing. 2003;7(5):299-308. doi:10.1007/s00779-003-0243-x
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2003 | Conference Paper | LibreCat-ID: 2421
Enzler R, Plessl C, Platzner M. Virtualizing Hardware with Multi-Context Reconfigurable Arrays. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Vol 2778. Lecture Notes in Computer Science (LNCS). Springer; 2003:151-160. doi:10.1007/b12007
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2003 | Conference Paper | LibreCat-ID: 13612
Walder H, Platzner M. Online scheduling for block-partitioned reconfigurable devices. In: Proceedings Design, Automation and Test in Europe Conference (DATE). IEEE CS Press; 2003:290-295. doi:10.1109/date.2003.1253622
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2003 | Conference Paper | LibreCat-ID: 13617
Steiger C, Walder H, Platzner M, Thiele L. Online scheduling and placement of real-time tasks to partially reconfigurable devices. In: Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS). IEEE CS Press; 2003:252-235. doi:10.1109/real.2003.1253269
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2003 | Conference Paper | LibreCat-ID: 2422
Enzler R, Plessl C, Platzner M. Co-simulation of a Hybrid Multi-Context Architecture. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2003:174-180.
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2003 | Conference Paper | LibreCat-ID: 13613
Walder H, Steiger C, Platzner M. Fast online task placement on FPGAs: free space partitioning and 2D-hashing. In: Proceedings International Parallel and Distributed Processing Symposium. IEEE CS Press; 2003. doi:10.1109/ipdps.2003.1213329
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2002 | Conference Paper | LibreCat-ID: 2424
Dyer M, Plessl C, Platzner M. Partially Reconfigurable Cores for Xilinx Virtex. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). Vol 2438. Lecture Notes in Computer Science (LNCS). Springer; 2002:292-301. doi:10.1007/3-540-46117-5
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2002 | Conference Paper | LibreCat-ID: 2425
Plessl C, Platzner M. Custom Computing Machines for the Set Covering Problem. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2002:163-172. doi:10.1109/FPGA.2002.1106671
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2002 | Conference Paper | LibreCat-ID: 13611
Walder H, Platzner M. Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform. In: Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2002:24-30.
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2002 | Journal Article | LibreCat-ID: 10651
Eisenring M, Platzner M. A Framework for Run-time Reconfigurable Systems. The Journal of Supercomputing. 2002;21(2):145-159. doi:10.1023/a:1013627403946
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2002 | Conference Paper | LibreCat-ID: 2423
Plessl C, Enzler R, Walder H, Beutel J, Platzner M, Thiele L. Reconfigurable Hardware in Wearable Computing Nodes. In: Proc. Int. Symp. on Wearable Computers (ISWC). IEEE Computer Society; 2002:215-222. doi:10.1109/ISWC.2002.1167250
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2001 | Misc | LibreCat-ID: 13463
Enzler R, Platzner M. Dynamically Reconfigurable Processors. TELEMATIK, Zeitschrift des Telematik-Ingebieur-Verbandes 7(1); 2001.
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2001 | Conference Paper | LibreCat-ID: 2432
Enzler R, Platzner M, Plessl C, Thiele L, Tröster G. Reconfigurable Processors for Handhelds and Wearables: Application Analysis. In: Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III. Vol 4525. Proc. SPIE. ; 2001:135-146. doi:10.1117/12.434376
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2001 | Journal Article | LibreCat-ID: 10713
Mencer O, Platzner M, Morf M, J. Flynn M. Object-oriented domain specific compilers for programming FPGAs. {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems. 2001;9(1):205-210. doi:10.1109/92.920835
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2001 | Conference Paper | LibreCat-ID: 2428
Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2001:85-91.
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2000 | Conference Paper | LibreCat-ID: 13610
Eisenring M, Platzner M. Optimization of Run-time Reconfigurable Embedded Systems. In: Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL). Springer; 2000:565-574.
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2000 | Journal Article | LibreCat-ID: 10725
Platzner M, Rinner B, Weiss R. Toward embedded qualitative simulation: a specialized computer architecture for QSim. IEEE Intelligent Systems. 2000;15(2):62-68. doi:10.1109/5254.850829
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2000 | Conference Paper | LibreCat-ID: 13609
Eisenring MH, Platzner M. An Implementation Framework for Run-time Reconfigurable Systems. In: Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE). CSREA Press; 2000:151-157.
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2000 | Journal Article | LibreCat-ID: 10606
Eisenring M, Platzner M. Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems. IEE Proceedings -- Computers & Digital Techniques. 2000;147:159-165. doi:10.1049/ip-cdt:20000496
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2000 | Journal Article | LibreCat-ID: 6507
Platzner M. Reconfigurable accelerators for combinatorial problems. Computer. 2000;33(4):58-60. doi:10.1109/2.839322
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1999 | Conference Paper | LibreCat-ID: 13607
Mencer O, Platzner M. Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment. In: Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32). IEEE CS Press; 1999. doi:10.1109/hicss.1999.772883
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1999 | Conference Paper | LibreCat-ID: 13608
Eisenring M, Platzner M, Thiele L. Communication Synthesis for Reconfigurable Embedded Systems. In: Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL). Vol 1673. LCS. Springer; 1999:205-214. doi:10.1007/978-3-540-48302-1_21
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1998 | Journal Article | LibreCat-ID: 10608
Platzner M, Rinner B. Design and Implementation of a Parallel Constraint Satisfaction Algorithm. International Journal of Computers & Their Applications. 1998;5:106-116.
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1998 | Misc | LibreCat-ID: 13464
Platzner M, Rinner B, Weiss R. A Distributed Computer Architecture for Fast Qualitative Simulation . Texas Instruments, The Elite Yearbook 1997 - Digital Signal Processing Solutions from Europe’s leading Universities; 1998:106-107.
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1998 | Journal Article | LibreCat-ID: 10607
Platzner M. Reconfigurable Computer Architectures. e&i Elektrotechnik und Informationstechnik. 1998;115:143-148.
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1998 | Conference Paper | LibreCat-ID: 13606
Platzner M, De Micheli G. Acceleration of satisfiability algorithms by reconfigurable hardware. In: Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL) . LNCS. Berlin, Heidelberg: Springer ; 1998:69-78. doi:10.1007/bfb0055234
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1997 | Journal Article | LibreCat-ID: 10609
Platzner M, Rinner B, Weiss R. A Computer Architecture to Support Qualitative Simulation in Industrial Applications. e & i Elektrotechnik und Informationstechnik. 1997;114:13-18.
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1997 | Journal Article | LibreCat-ID: 10724
Platzner M, Rinner B, Weiss R. Parallel qualitative simulation. Simulation Practice and Theory. 1997;5(7-8):623-638. doi:10.1016/s0928-4869(97)00008-6
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1997 | Conference Paper | LibreCat-ID: 13603
Platzner M, Peters L. Fast Signature Segmentation on a Multi-DSP Architecture. In: Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing. Vol 3166. ; 1997.
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1997 | Conference Paper | LibreCat-ID: 13604
Röwekamp T, Platzner M, Peters L. Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP. In: Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT). ; 1997:829-833.
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1996 | Conference Paper | LibreCat-ID: 13602
Lind E, Platzner M, Rinner B. A Multi-DSP System with Dynamically Reconfigurable Processors. In: Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT). ; 1996.
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1995 | Journal Article | LibreCat-ID: 10610
Platzner M, Rinner B, Weiss R. Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation. JUCS Journal of Universal Computer Science. 1995;12:811-820.
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1995 | Conference Paper | LibreCat-ID: 13474
Platzner M, Rinner B. High-Performance Qualitative Simulation on a Multi-DSP Architecture. In: Proceedings of the 6th International Conference on Signal Processing Applications & Technology (ICSPAT). ; 1995.
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1995 | Conference Paper | LibreCat-ID: 13470
Brenner E, Ginthör-Kalcsics R, Hranitzky R, et al. High-Performance Simulators Based on Multi-TMS320C40. In: Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference. ; 1995.
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1995 | Conference Paper | LibreCat-ID: 13469
Platzner M, Rinner B, Weiss R. A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs. In: Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing . IEEE CS Press; 1995:311-318.
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1995 | Conference Paper | LibreCat-ID: 13471
Friedl G, Platzner M, Rinner B. A Special-Purpose Coprocessor for Qualitative Simulation. In: Proceedings of the EURO-PAR’95 International Conference on Parallel Processing. Springer International Publishing; 1995:695-698.
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1995 | Conference Paper | LibreCat-ID: 13472
Platzner M, Rinner B, Weiss R. Parallel Qualitative Simulation. In: Proceedings of the EUROSIM Congress. Elsevier; 1995:231-236.
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1995 | Conference Paper | LibreCat-ID: 13484
Hranitzky R, Platzner M. Design and Implementation of Adaptive Digital Filters on a Multi-TMS320C40 System. In: Proceedings of the 6th International Conference on Signal Processing Applications & Technology (ICSPAT). ; 1995.
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1995 | Conference Paper | LibreCat-ID: 13473
Platzner M, Rinner B. Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture. In: Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems. ISCA; 1995:494-501.
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1994 | Conference Paper | LibreCat-ID: 13468
Platzner M, Steger C, Weiss R. Experimental Evaluation of Multi-DSP Architectures in High Performance Applications. In: Proceedings of the 7th Mediterranean Electrotechnical Conference. IEEE Press; 1994.
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1993 | Conference Paper | LibreCat-ID: 13467
Platzner M, Steger C, Weiss R. Performance Measurements on a Multi-DSP Architecture with TMS320C40. In: Proceedings of the 4th International Conference on Signal Processing Applications & Technology (ICSPAT). DSP Associates; 1993.
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1993 | Journal Article | LibreCat-ID: 13466
Platzner M, Steger C. Erfahrungen mit einer Multi-Signalprozessorarchitektur (TMS320C40). Mikroelektronik. 1993.
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1992 | Conference Paper | LibreCat-ID: 13465
Ginthör R, Platzner M, Weiss R. Experimental Results to Interprocessor Communication in Distributed Transputer-Systems. In: Proceedings of the 1st Austrian-Hungarian Workshop on Transputer Applications. ; 1992:45-54.
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