9 Publications

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[9]
2021 | Journal Article | LibreCat-ID: 29210
Wu, L., & Scheytt, J. C. (2021). Analysis and Design of a Charge Sampler With 70-GHz 1-dB Bandwidth in 130-nm SiGe BiCMOS. IEEE Transactions on Circuits and Systems I: Regular Papers, 68(9), 3668–3681. https://doi.org/10.1109/tcsi.2021.3094428
LibreCat | Files available | DOI
 
[8]
2020 | Conference Paper | LibreCat-ID: 24021
Wu, L., Weizel, M., & Scheytt, C. (2020). Above 60 GHz Bandwidth 10 GS/s Sampling Rate Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology. 2020 IEEE International Symposium on Circuits and Systems (ISCAS). https://doi.org/10.1109/ISCAS45731.2020.9180947
LibreCat | Files available | DOI
 
[7]
2019 | Conference Paper | LibreCat-ID: 24049
Wu, L., Weizel, M., & Scheytt, C. (2019). 70 GHz Large-signal Bandwidth Sampler Using Current-mode Integrate-and-Hold Circuit in 130 nm SiGe BiCMOS Technology. Asia-Pacific Microwave Conference (APMC). https://doi.org/10.1109/APMC46564.2019.9038239
LibreCat | Files available | DOI
 
[6]
2019 | Conference Paper | LibreCat-ID: 24052
Wu, L., Weizel, M., & Scheytt, C. (2019). A 70 GHz Small-signal Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology. 26th IEEE International Conference on Electronics Circuits and Systems (ICECS). https://doi.org/10.1109/ICECS46596.2019.8965046
LibreCat | Files available | DOI
 
[5]
2018 | Conference Paper | LibreCat-ID: 24196
Wu, L., Hussain, M. K., Abughannam, S., Müller, W., Scheytt, C., & Ecker, W. (2018). Analog fault simulation automation at schematic level with random sampling techniques. 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)) . https://doi.org/10.1109/DTIS.2018.8368549
LibreCat | Files available | DOI
 
[4]
2018 | Patent | LibreCat-ID: 24198
Scheytt, C., & Wu, L. (2018). Integrier‐ und Halte‐Schaltung .
LibreCat | Files available
 
[3]
2017 | Conference Paper | LibreCat-ID: 24223
Wu, L., Abughannam, S., Müller, W., Scheytt, C., & Ecker, W. (2017). SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study. 2nd Workshop on Resiliency in Embedded Electronic Systems (REES), 68.
LibreCat | Files available
 
[2]
2016 | Conference Paper | LibreCat-ID: 24263
Abughannam, S., Wu, L., Müller, W., & Scheytt, C. (2016). Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study. Analog 2016 - VDE.
LibreCat
 
[1]
2015 | Conference Paper | LibreCat-ID: 24289
Müller, W., Wu, L., Scheytt, C., Becker, M., & Schoenberg, S. (2015). On the Correlation of HW Faults and SW Errors. In D. Mueller-Gritschneder, W. Müller, & S. Mitra (Eds.), Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014).
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9 Publications

Mark all

[9]
2021 | Journal Article | LibreCat-ID: 29210
Wu, L., & Scheytt, J. C. (2021). Analysis and Design of a Charge Sampler With 70-GHz 1-dB Bandwidth in 130-nm SiGe BiCMOS. IEEE Transactions on Circuits and Systems I: Regular Papers, 68(9), 3668–3681. https://doi.org/10.1109/tcsi.2021.3094428
LibreCat | Files available | DOI
 
[8]
2020 | Conference Paper | LibreCat-ID: 24021
Wu, L., Weizel, M., & Scheytt, C. (2020). Above 60 GHz Bandwidth 10 GS/s Sampling Rate Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology. 2020 IEEE International Symposium on Circuits and Systems (ISCAS). https://doi.org/10.1109/ISCAS45731.2020.9180947
LibreCat | Files available | DOI
 
[7]
2019 | Conference Paper | LibreCat-ID: 24049
Wu, L., Weizel, M., & Scheytt, C. (2019). 70 GHz Large-signal Bandwidth Sampler Using Current-mode Integrate-and-Hold Circuit in 130 nm SiGe BiCMOS Technology. Asia-Pacific Microwave Conference (APMC). https://doi.org/10.1109/APMC46564.2019.9038239
LibreCat | Files available | DOI
 
[6]
2019 | Conference Paper | LibreCat-ID: 24052
Wu, L., Weizel, M., & Scheytt, C. (2019). A 70 GHz Small-signal Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology. 26th IEEE International Conference on Electronics Circuits and Systems (ICECS). https://doi.org/10.1109/ICECS46596.2019.8965046
LibreCat | Files available | DOI
 
[5]
2018 | Conference Paper | LibreCat-ID: 24196
Wu, L., Hussain, M. K., Abughannam, S., Müller, W., Scheytt, C., & Ecker, W. (2018). Analog fault simulation automation at schematic level with random sampling techniques. 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)) . https://doi.org/10.1109/DTIS.2018.8368549
LibreCat | Files available | DOI
 
[4]
2018 | Patent | LibreCat-ID: 24198
Scheytt, C., & Wu, L. (2018). Integrier‐ und Halte‐Schaltung .
LibreCat | Files available
 
[3]
2017 | Conference Paper | LibreCat-ID: 24223
Wu, L., Abughannam, S., Müller, W., Scheytt, C., & Ecker, W. (2017). SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study. 2nd Workshop on Resiliency in Embedded Electronic Systems (REES), 68.
LibreCat | Files available
 
[2]
2016 | Conference Paper | LibreCat-ID: 24263
Abughannam, S., Wu, L., Müller, W., & Scheytt, C. (2016). Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study. Analog 2016 - VDE.
LibreCat
 
[1]
2015 | Conference Paper | LibreCat-ID: 24289
Müller, W., Wu, L., Scheytt, C., Becker, M., & Schoenberg, S. (2015). On the Correlation of HW Faults and SW Errors. In D. Mueller-Gritschneder, W. Müller, & S. Mitra (Eds.), Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014).
LibreCat
 

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