10 Publications
2021 | Journal Article | LibreCat-ID: 29210
L. Wu and J. C. Scheytt, “Analysis and Design of a Charge Sampler With 70-GHz 1-dB Bandwidth in 130-nm SiGe BiCMOS,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 9, pp. 3668–3681, 2021, doi: 10.1109/tcsi.2021.3094428.
LibreCat
| Files available
| DOI
2021 | Dissertation | LibreCat-ID: 52664
L. Wu, Ultrabreitbandige Sampler in SiGe-BiCMOS-Technologie für Analog-Digital-Wandler mit zeitversetzter Abtastung, vol. 402. 2021.
LibreCat
2020 | Conference Paper | LibreCat-ID: 24021
L. Wu, M. Weizel, and C. Scheytt, “Above 60 GHz Bandwidth 10 GS/s Sampling Rate Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology,” 2020, doi: 10.1109/ISCAS45731.2020.9180947.
LibreCat
| DOI
2019 | Conference Paper | LibreCat-ID: 24052
L. Wu, M. Weizel, and C. Scheytt, “A 70 GHz Small-signal Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology,” 2019, doi: 10.1109/ICECS46596.2019.8965046.
LibreCat
| DOI
2019 | Conference Paper | LibreCat-ID: 24049
L. Wu, M. Weizel, and C. Scheytt, “70 GHz Large-signal Bandwidth Sampler Using Current-mode Integrate-and-Hold Circuit in 130 nm SiGe BiCMOS Technology,” Singapore , 2019, doi: 10.1109/APMC46564.2019.9038239.
LibreCat
| DOI
2018 | Conference Paper | LibreCat-ID: 24196
L. Wu, M. K. Hussain, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker, “Analog fault simulation automation at schematic level with random sampling techniques,” 2018, doi: 10.1109/DTIS.2018.8368549.
LibreCat
| Files available
| DOI
2018 | Patent | LibreCat-ID: 24198
C. Scheytt and L. Wu, “Integrier‐ und Halte‐Schaltung .” 2018.
LibreCat
| Files available
2017 | Conference Paper | LibreCat-ID: 24223
L. Wu, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker, “SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study,” in 2nd Workshop on Resiliency in Embedded Electronic Systems (REES), 2017, p. 68.
LibreCat
| Files available
2016 | Conference Paper | LibreCat-ID: 24263
S. Abughannam, L. Wu, W. Müller, C. Scheytt, W. Ecker, and C. Novello, “Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study,” 2016.
LibreCat
| Files available
2015 | Conference Paper | LibreCat-ID: 24289
W. Müller, L. Wu, C. Scheytt, M. Becker, and S. Schoenberg, “On the Correlation of HW Faults and SW Errors,” in Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014), 2015.
LibreCat
10 Publications
2021 | Journal Article | LibreCat-ID: 29210
L. Wu and J. C. Scheytt, “Analysis and Design of a Charge Sampler With 70-GHz 1-dB Bandwidth in 130-nm SiGe BiCMOS,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 9, pp. 3668–3681, 2021, doi: 10.1109/tcsi.2021.3094428.
LibreCat
| Files available
| DOI
2021 | Dissertation | LibreCat-ID: 52664
L. Wu, Ultrabreitbandige Sampler in SiGe-BiCMOS-Technologie für Analog-Digital-Wandler mit zeitversetzter Abtastung, vol. 402. 2021.
LibreCat
2020 | Conference Paper | LibreCat-ID: 24021
L. Wu, M. Weizel, and C. Scheytt, “Above 60 GHz Bandwidth 10 GS/s Sampling Rate Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology,” 2020, doi: 10.1109/ISCAS45731.2020.9180947.
LibreCat
| DOI
2019 | Conference Paper | LibreCat-ID: 24052
L. Wu, M. Weizel, and C. Scheytt, “A 70 GHz Small-signal Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology,” 2019, doi: 10.1109/ICECS46596.2019.8965046.
LibreCat
| DOI
2019 | Conference Paper | LibreCat-ID: 24049
L. Wu, M. Weizel, and C. Scheytt, “70 GHz Large-signal Bandwidth Sampler Using Current-mode Integrate-and-Hold Circuit in 130 nm SiGe BiCMOS Technology,” Singapore , 2019, doi: 10.1109/APMC46564.2019.9038239.
LibreCat
| DOI
2018 | Conference Paper | LibreCat-ID: 24196
L. Wu, M. K. Hussain, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker, “Analog fault simulation automation at schematic level with random sampling techniques,” 2018, doi: 10.1109/DTIS.2018.8368549.
LibreCat
| Files available
| DOI
2018 | Patent | LibreCat-ID: 24198
C. Scheytt and L. Wu, “Integrier‐ und Halte‐Schaltung .” 2018.
LibreCat
| Files available
2017 | Conference Paper | LibreCat-ID: 24223
L. Wu, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker, “SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study,” in 2nd Workshop on Resiliency in Embedded Electronic Systems (REES), 2017, p. 68.
LibreCat
| Files available
2016 | Conference Paper | LibreCat-ID: 24263
S. Abughannam, L. Wu, W. Müller, C. Scheytt, W. Ecker, and C. Novello, “Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study,” 2016.
LibreCat
| Files available
2015 | Conference Paper | LibreCat-ID: 24289
W. Müller, L. Wu, C. Scheytt, M. Becker, and S. Schoenberg, “On the Correlation of HW Faults and SW Errors,” in Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014), 2015.
LibreCat