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264 Publications
2024 | Conference Paper | LibreCat-ID: 45778
L. Luchterhandt et al., “Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells,” presented at the MBMV 2023 - 26. Workshop, Freiburg, , Germany, Freiburg, 2024.
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2024 | Conference Paper | LibreCat-ID: 53579
P. Palomero Bernardo et al., “A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing,” Valencia, Spain, 2024.
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2023 | Conference Paper | LibreCat-ID: 45775
L. Luchterhandt et al., “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture,” presented at the MBMV 2023, Freiburg, Freiburg, 2023.
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2023 | Conference Paper | LibreCat-ID: 45776
W. Ecker et al., “Scale4Edge – Scaling RISC-V for Edge Applications,” presented at the RISC-V Summit Europe 2023, Barcelona, Spain, June 2023., Barcelona, Spain, 2023.
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2023 | Conference Paper | LibreCat-ID: 48530
W. Müller, M. Ulbricht, L. Li, and M. Krstic, “Der TETRISC SoC - Ein resilientes Quad-Core System auf Pulpissimo-Basis,” presented at the 5. ITG / GMM / GI -Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen , Erfurt. Germany, 2023.
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2023 | Conference Abstract | LibreCat-ID: 48961
M. Iftekhar, H. Gowda, P. Kneuper, B. Sadiye, W. Müller, and C. Scheytt, “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology,” presented at the 2023 IEEE BiCMOS und Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), Monterey, CA, USA, 2023, doi: 10.1109/BCICTS54660.2023.10310954.
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2022 | Conference Paper | LibreCat-ID: 29302
W. Ecker et al., “The Scale4Edge RISC-V Ecosystem,” 2022.
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2021 | Conference Paper | LibreCat-ID: 32125
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules,” 2021.
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2021 | Conference Paper | LibreCat-ID: 32132
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU zur Simulation von Worst-Case-Ausführungszeiten,” 2021.
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2021 | Conference Paper | LibreCat-ID: 23992
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules,” 2021.
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2020 | Conference Paper | LibreCat-ID: 24027
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures,” 2020.
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2019 | Conference Paper | LibreCat-ID: 24058
B. Koppelmann, P. Adelt, W. Müller, and C. Scheytt, “RISC-V Extensions for Bit Manipulation Instructions,” 2019, doi: 10.1109/PATMOS.2019.8862170.
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2019 | Conference Paper | LibreCat-ID: 24060
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Analyse sicherheitskritischer Software für RISC-V Prozessoren,” 2019.
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2019 | Conference Paper | LibreCat-ID: 24061
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, and B. Driessen, “QEMU for Dynamic Memory Analysis of Security Sensitive Software,” in 2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019, 2019, pp. 32–34.
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2019 | Journal Article | LibreCat-ID: 24063
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU Support for RISC-V: Current State and Future Releases,” 2nd International Workshop on RISC-V Research Activities, vol. (Presentation), 2019.
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2019 | Book (Editor) | LibreCat-ID: 53596
O. Bringmann, W. Ecker, W. Müller, and D. Müller-Gridschneder, Eds., Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT. Florence, Italy, 2019.
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2018 | Journal Article | LibreCat-ID: 24194
P. Adelt, B. Koppelmann, and W. Müller, “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design,” International Workshop on RISC-V Research Activities, vol. Presentation, 2018.
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2018 | Conference Paper | LibreCat-ID: 24196
L. Wu, M. K. Hussain, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker, “Analog fault simulation automation at schematic level with random sampling techniques,” 2018, doi: 10.1109/DTIS.2018.8368549.
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2018 | Book (Editor) | LibreCat-ID: 53595
O. Bringmann, W. Ecker, W. Müller, and D. Müller-Gridschneder, Eds., Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT. Dresden, Germany, 2018.
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2017 | Conference Paper | LibreCat-ID: 24220
P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann, and C. Scheytt, “Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen,” 2017, doi: 10.17619/UNIPB/1-93.
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2017 | Conference Paper | LibreCat-ID: 24223
L. Wu, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker, “SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study,” in 2nd Workshop on Resiliency in Embedded Electronic Systems (REES), 2017, p. 68.
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2017 | Conference Paper | LibreCat-ID: 24224
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and C. Scheytt, “ANALISA - A Tool for Static Instruction Set Analysis,” 2017.
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2017 | Conference Paper | LibreCat-ID: 24225
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and C. Scheytt, “An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries,” in 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) , 2017, p. 44.
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2016 | Conference Paper | LibreCat-ID: 24264
P. Adelt, B. Koppelmann, W. Müller, M. Becker, B. Kleinjohann, and C. Scheytt, “Fast Dynamic Fault Injection for Virtual Microcontroller Platforms,” 2016, doi: 10.1109/VLSI-SoC.2016.7753545.
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2016 | Conference Paper | LibreCat-ID: 24263
S. Abughannam, L. Wu, W. Müller, C. Scheytt, W. Ecker, and C. Novello, “Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study,” 2016.
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2015 | Conference Paper | LibreCat-ID: 24289
W. Müller, L. Wu, C. Scheytt, M. Becker, and S. Schoenberg, “On the Correlation of HW Faults and SW Errors,” in Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014), 2015.
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2015 | Book (Editor) | LibreCat-ID: 53590
D. Müller-Gridschneder, W. Müller, and S. Mitra, Eds., Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems. Amsterdam, Netherlands, 2015.
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2014 | Conference Paper | LibreCat-ID: 25145
M. Becker, C. Kuznik, and W. Müller, “Virtual Platforms for Model-Based Design of Dependable Cyber-Physical System Software,” 2014.
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2014 | Conference Paper | LibreCat-ID: 25155
M. Becker, C. Kuznik, and W. Müller, “Fault Effect Modeling in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems,” 2014.
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2014 | Conference Paper | LibreCat-ID: 25161
B. Koppelmann, M. Becker, and W. Müller, “Portierung der TriCore-Architektur auf QEMU,” 2014.
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2014 | Conference Paper | LibreCat-ID: 24305
F. Mischkalla and W. Müller, “Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation,” 2014, doi: 10.1109/SAMOS.2014.6893219.
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2014 | Journal Article | LibreCat-ID: 24302
B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, and C. Scheytt, “Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” Design and Verification Conference (DVCON EUROPE), 2014.
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2014 | Journal Article | LibreCat-ID: 24309
C. Kuznik and W. Müller, “Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure,” Design, Automation and Test in Europe DATE, University Booth, Dresden, 2014.
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2014 | Conference Paper | LibreCat-ID: 24311
J.-H. Oetjens et al., “Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges,” 2014, doi: 10.1145/2593069.2602976.
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2014 | Conference Paper | LibreCat-ID: 25120
F. Mischkalla and W. Müller, “Architectural Low-Power Design Using Transaction-Based System Simulation,” Greece, Sep. 2014, IEEE, 2014.
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2014 | Conference Paper | LibreCat-ID: 25146
M. tech. M. M. Joy, W. Müller, and F.-J. Rammig, “Source code annotated memory leak detection for soft real time embedded systems with resource constraints,” 2014.
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2014 | Conference Paper | LibreCat-ID: 25144
F. Mischkalla and W. Müller, “Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation,” 2014.
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2014 | Conference Paper | LibreCat-ID: 36918
M. Becker, C. Kuznik, and W. Müller, “Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems,” presented at the ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS), Berlin, 2014, doi: 10.1109/ICCPS.2014.6843726.
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2014 | Conference Paper | LibreCat-ID: 36917
C. Kuznik, W. Müller, and G. B. Defo, “An Assisted Single Source Verification Metric Model Code Generation Methodology,” presented at the Proceedings of the Electronic System Level Synthesis Conference (ESLSyn), 2014.
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2014 | Conference Paper | LibreCat-ID: 25166
C. Kuznik and W. Müller, “Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM,” 2014.
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2014 | Conference Paper | LibreCat-ID: 25163
C. Kuznik, B. G. Defo, and W. Müller, “Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung,” 2014.
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2014 | Journal Article | LibreCat-ID: 25151
C. Kuznik, B. G. Defo, and W. Müller, “An Assisted Single Source Verification Metric Model Code Generation Methodology,” Electronic System Level Synthesis Conference (ESLSyn), 2014.
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2014 | Conference Paper | LibreCat-ID: 34585
B. Koppelmann, B. Messidat, M. Becker, W. Müller, and J. C. Scheytt, “Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” 2014.
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2014 | Journal Article | LibreCat-ID: 25164
M. Becker, W. Müller, J. Stroop, and U. Kiffmeier, “HeroeS - A Framework for Heterogeneous Software-Intensive System Design with SystemC,” Design, Automation and Test in Europe DATE, University Booth, Dresden, 2014.
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2013 | Conference Paper | LibreCat-ID: 25270
M. tech. M. M. Joy, W. Müller, and F.-J. Rammig, “Early Phase Memory Leak Detection in Embedded Software Designs with Virtual Memory Management Model,” 2013.
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2013 | Conference Paper | LibreCat-ID: 25271
D. He and W. Müller, “AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS,” 2013.
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2013 | Conference Paper | LibreCat-ID: 25284
F. Mischkalla and W. Müller, “ Efficient Power Intent Validation Using Loosely-Timed Simulation Models,” 2013.
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2013 | Conference Paper | LibreCat-ID: 25291
M. Becker, U. Kiffmeier, and W. Müller, “HeroeS: Virtual Platform Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time Architectures,” 2013.
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2013 | Conference Paper | LibreCat-ID: 25606
C. Kuznik, M. F. S. Oliveira, and W. Müller, “SystemC Verification Components - An enhanced OVM/UVM for SystemC,” Mrz. 2013 - Poster, 2013.
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2013 | Conference Paper | LibreCat-ID: 25612
F. Mischkalla and W. Müller, “Funktionale Verifikation von Low-Power Designs unter Verwendung Virtueller Prototypen,” 2013.
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