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264 Publications
2024 | Conference Paper | LibreCat-ID: 45778
Luchterhandt, Lars, et al. “Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells.” MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, VDE Verlag, 2024.
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2024 | Conference Paper | LibreCat-ID: 53579
Palomero Bernardo, Paul, et al. “A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing.” DATE 24 - Design Automation and Test in Europe, 2024.
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2023 | Conference Paper | LibreCat-ID: 45775
Luchterhandt, Lars, et al. “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture.” MBMV 2023 - 26. Workshop "Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg, VDE Verlag, 2023.
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2023 | Conference Paper | LibreCat-ID: 45776
Ecker, Wolfgang, et al. “Scale4Edge – Scaling RISC-V for Edge Applications.” RISC-V Summit Europe 2023, Barcelona, Spain, June 2023., 2023.
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2023 | Conference Paper | LibreCat-ID: 48530
Müller, Wolfgang, et al. “Der TETRISC SoC - Ein Resilientes Quad-Core System Auf Pulpissimo-Basis.” 5. ITG / GMM / GI -Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen , 2023.
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2023 | Conference Abstract | LibreCat-ID: 48961
Iftekhar, Mohammed, et al. “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 Nm FD-SOI CMOS Technology.” 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2023, doi:10.1109/BCICTS54660.2023.10310954.
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2022 | Conference Paper | LibreCat-ID: 29302
Ecker, Wolfgang, et al. “The Scale4Edge RISC-V Ecosystem.” In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022), 2022.
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2021 | Conference Paper | LibreCat-ID: 32125
Adelt, Peer, et al. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, 2021.
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2021 | Conference Paper | LibreCat-ID: 32132
Adelt, Peer, et al. “QEMU zur Simulation von Worst-Case-Ausführungszeiten.” MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, 2021.
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2021 | Conference Paper | LibreCat-ID: 23992
Adelt, Peer, et al. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021), 2021.
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2020 | Conference Paper | LibreCat-ID: 24027
Adelt, Peer, et al. “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures.” MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, 2020.
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2019 | Conference Paper | LibreCat-ID: 24058
Koppelmann, Bastian, et al. “RISC-V Extensions for Bit Manipulation Instructions.” 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2019, doi:10.1109/PATMOS.2019.8862170.
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2019 | Conference Paper | LibreCat-ID: 24060
Adelt, Peer, et al. “Analyse Sicherheitskritischer Software Für RISC-V Prozessoren.” MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019), 2019.
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2019 | Conference Paper | LibreCat-ID: 24061
Adelt, Peer, et al. “QEMU for Dynamic Memory Analysis of Security Sensitive Software.” 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019, 2019, pp. 32–34.
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2019 | Journal Article | LibreCat-ID: 24063
Adelt, Peer, et al. “QEMU Support for RISC-V: Current State and Future Releases.” 2nd International Workshop on RISC-V Research Activities, vol. (Presentation), 2019.
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2019 | Book (Editor) | LibreCat-ID: 53596
Bringmann, Oliver, et al., editors. Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT. 2019.
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2018 | Journal Article | LibreCat-ID: 24194
Adelt, Peer, et al. “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design.” International Workshop on RISC-V Research Activities, vol. Presentation, 2018.
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2018 | Conference Paper | LibreCat-ID: 24196
Wu, Liang, et al. “Analog Fault Simulation Automation at Schematic Level with Random Sampling Techniques.” 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)) , IEEE, 2018, doi:10.1109/DTIS.2018.8368549.
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2018 | Book (Editor) | LibreCat-ID: 53595
Bringmann, Oliver, et al., editors. Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT. 2018.
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2017 | Conference Paper | LibreCat-ID: 24220
Adelt, Peer, et al. “Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen.” Tagungsband des Wissenschaftsforums Intelligente Technische Systeme, Verlagsschriftenreihe des Heinz Nixdorf Instituts, 2017, doi:10.17619/UNIPB/1-93.
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2017 | Conference Paper | LibreCat-ID: 24223
Wu, Liang, et al. “SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study.” 2nd Workshop on Resiliency in Embedded Electronic Systems (REES), 2017, p. 68.
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2017 | Conference Paper | LibreCat-ID: 24224
Adelt, Peer, et al. “ANALISA - A Tool for Static Instruction Set Analysis.” Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation, 2017.
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2017 | Conference Paper | LibreCat-ID: 24225
Adelt, Peer, et al. “An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries.” 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) , 2017, p. 44.
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2016 | Conference Paper | LibreCat-ID: 24264
Adelt, Peer, et al. “Fast Dynamic Fault Injection for Virtual Microcontroller Platforms.” Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC), 2016, doi:10.1109/VLSI-SoC.2016.7753545.
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2016 | Conference Paper | LibreCat-ID: 24263
Abughannam, Saed, et al. “Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study.” Analog 2016 - VDE, 2016.
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2015 | Conference Paper | LibreCat-ID: 24289
Müller, Wolfgang, et al. “On the Correlation of HW Faults and SW Errors.” Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014), edited by Daniel Mueller-Gritschneder et al., 2015.
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2015 | Book (Editor) | LibreCat-ID: 53590
Müller-Gridschneder, Daniel, et al., editors. Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems. 2015.
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2014 | Conference Paper | LibreCat-ID: 25145
Becker, Markus, et al. “Virtual Platforms for Model-Based Design of Dependable Cyber-Physical System Software.” 17th Euromicro Conference on Digital Systems Design (DSD), 2014.
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2014 | Conference Paper | LibreCat-ID: 25155
Becker, Markus, et al. “Fault Effect Modeling in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems.” ACM/IEEE 5th International Conference on Cyber-Physical Systems, 2014.
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2014 | Conference Paper | LibreCat-ID: 25161
Koppelmann, Bastian, et al. “Portierung Der TriCore-Architektur Auf QEMU.” 17. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2014) , 2014.
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2014 | Conference Paper | LibreCat-ID: 24305
Mischkalla, Fabian, and Wolfgang Müller. “Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation.” Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), IEEE, 2014, doi:10.1109/SAMOS.2014.6893219.
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2014 | Journal Article | LibreCat-ID: 24302
Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” Design and Verification Conference (DVCON EUROPE), 2014.
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2014 | Journal Article | LibreCat-ID: 24309
Kuznik, Christoph, and Wolfgang Müller. “Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure.” Design, Automation and Test in Europe DATE, University Booth, Dresden, 2014.
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2014 | Conference Paper | LibreCat-ID: 24311
Oetjens, Jan-Hendrik, et al. “Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges.” Design Automation Conference (DAC), 2014, doi:10.1145/2593069.2602976.
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2014 | Conference Paper | LibreCat-ID: 25120
Mischkalla, Fabian, and Wolfgang Müller. “Architectural Low-Power Design Using Transaction-Based System Simulation.” Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), IEEE, 2014.
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2014 | Conference Paper | LibreCat-ID: 25146
Joy, M. tech. Mabel Mary, et al. “Source Code Annotated Memory Leak Detection for Soft Real Time Embedded Systems with Resource Constraints.” 12th IEEE International Conference on Embedded Computing, 2014.
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2014 | Conference Paper | LibreCat-ID: 25144
Mischkalla, Fabian, and Wolfgang Müller. “Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation.” PATMOS 2014, 2014.
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2014 | Conference Paper | LibreCat-ID: 36918
Becker, Markus, et al. Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems. IEEE, 2014, doi:10.1109/ICCPS.2014.6843726.
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2014 | Conference Paper | LibreCat-ID: 36917
Kuznik, Christoph, et al. An Assisted Single Source Verification Metric Model Code Generation Methodology. 2014.
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2014 | Conference Paper | LibreCat-ID: 25166
Kuznik, Christoph, and Wolfgang Müller. “Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM.” 26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, 2014.
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2014 | Conference Paper | LibreCat-ID: 25163
Kuznik, Christoph, et al. “Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung.” 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) , 2014.
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2014 | Journal Article | LibreCat-ID: 25151
Kuznik, Christoph, et al. “An Assisted Single Source Verification Metric Model Code Generation Methodology.” Electronic System Level Synthesis Conference (ESLSyn), 2014.
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2014 | Conference Paper | LibreCat-ID: 34585
Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” Proceedings of the Design and Verification Conference Europe (DVCON Europe), 2014.
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2014 | Journal Article | LibreCat-ID: 25164
Becker, Markus, et al. “HeroeS - A Framework for Heterogeneous Software-Intensive System Design with SystemC.” Design, Automation and Test in Europe DATE, University Booth, Dresden, 2014.
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2013 | Conference Paper | LibreCat-ID: 25270
Joy, M. tech. Mabel Mary, et al. “Early Phase Memory Leak Detection in Embedded Software Designs with Virtual Memory Management Model.” Proceedings of AVICPS 2013, Dez. 2013 IEEE Computer Society, Linköping University Electronic Press, 2013.
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2013 | Conference Paper | LibreCat-ID: 25271
He, Da, and Wolfgang Müller. “AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS.” Proceedings of International Conference on Applied Computing (AC), 2013.
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2013 | Conference Paper | LibreCat-ID: 25284
Mischkalla, Fabian, and Wolfgang Müller. “ Efficient Power Intent Validation Using Loosely-Timed Simulation Models.” 23rd International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep. 2013, 2013.
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2013 | Conference Paper | LibreCat-ID: 25291
Becker, Markus, et al. “HeroeS: Virtual Platform Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time Architectures.” 16th IEEE Computer Society Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2013.
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2013 | Conference Paper | LibreCat-ID: 25606
Kuznik, Christoph, et al. “SystemC Verification Components - An Enhanced OVM/UVM for SystemC.” EdaWorkshop 13, 2013.
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2013 | Conference Paper | LibreCat-ID: 25612
Mischkalla, Fabian, and Wolfgang Müller. “Funktionale Verifikation von Low-Power Designs unter Verwendung Virtueller Prototypen.” Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013.
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