Please note that LibreCat no longer supports Internet Explorer versions 8 or 9 (or earlier).
We recommend upgrading to the latest Internet Explorer, Google Chrome, or Firefox.
264 Publications
2024 | Conference Paper | LibreCat-ID: 45778
L. Luchterhandt et al., “Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells,” presented at the MBMV 2023 - 26. Workshop, Freiburg, , Germany, Freiburg, 2024.
LibreCat
| Files available
2024 | Conference Paper | LibreCat-ID: 53579
P. Palomero Bernardo et al., “A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing,” Valencia, Spain, 2024.
LibreCat
2023 | Conference Paper | LibreCat-ID: 45775
L. Luchterhandt et al., “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture,” presented at the MBMV 2023, Freiburg, Freiburg, 2023.
LibreCat
| Files available
2023 | Conference Paper | LibreCat-ID: 45776
W. Ecker et al., “Scale4Edge – Scaling RISC-V for Edge Applications,” presented at the RISC-V Summit Europe 2023, Barcelona, Spain, June 2023., Barcelona, Spain, 2023.
LibreCat
| Files available
2023 | Conference Paper | LibreCat-ID: 48530
W. Müller, M. Ulbricht, L. Li, and M. Krstic, “Der TETRISC SoC - Ein resilientes Quad-Core System auf Pulpissimo-Basis,” presented at the 5. ITG / GMM / GI -Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen , Erfurt. Germany, 2023.
LibreCat
2023 | Conference Abstract | LibreCat-ID: 48961
M. Iftekhar, H. Gowda, P. Kneuper, B. Sadiye, W. Müller, and C. Scheytt, “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology,” presented at the 2023 IEEE BiCMOS und Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), Monterey, CA, USA, 2023, doi: 10.1109/BCICTS54660.2023.10310954.
LibreCat
| Files available
| DOI
2022 | Conference Paper | LibreCat-ID: 29302
W. Ecker et al., “The Scale4Edge RISC-V Ecosystem,” 2022.
LibreCat
2021 | Conference Paper | LibreCat-ID: 32125
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules,” 2021.
LibreCat
| Files available
2021 | Conference Paper | LibreCat-ID: 32132
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU zur Simulation von Worst-Case-Ausführungszeiten,” 2021.
LibreCat
2021 | Conference Paper | LibreCat-ID: 23992
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules,” 2021.
LibreCat
2020 | Conference Paper | LibreCat-ID: 24027
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures,” 2020.
LibreCat
| Files available
2019 | Conference Paper | LibreCat-ID: 24058
B. Koppelmann, P. Adelt, W. Müller, and C. Scheytt, “RISC-V Extensions for Bit Manipulation Instructions,” 2019, doi: 10.1109/PATMOS.2019.8862170.
LibreCat
| Files available
| DOI
2019 | Conference Paper | LibreCat-ID: 24060
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “Analyse sicherheitskritischer Software für RISC-V Prozessoren,” 2019.
LibreCat
| Files available
2019 | Conference Paper | LibreCat-ID: 24061
P. Adelt, B. Koppelmann, W. Müller, C. Scheytt, and B. Driessen, “QEMU for Dynamic Memory Analysis of Security Sensitive Software,” in 2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019, 2019, pp. 32–34.
LibreCat
| Files available
2019 | Journal Article | LibreCat-ID: 24063
P. Adelt, B. Koppelmann, W. Müller, and C. Scheytt, “QEMU Support for RISC-V: Current State and Future Releases,” 2nd International Workshop on RISC-V Research Activities, vol. (Presentation), 2019.
LibreCat
| Files available
2019 | Book (Editor) | LibreCat-ID: 53596
O. Bringmann, W. Ecker, W. Müller, and D. Müller-Gridschneder, Eds., Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT. Florence, Italy, 2019.
LibreCat
2018 | Journal Article | LibreCat-ID: 24194
P. Adelt, B. Koppelmann, and W. Müller, “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design,” International Workshop on RISC-V Research Activities, vol. Presentation, 2018.
LibreCat
| Files available
2018 | Conference Paper | LibreCat-ID: 24196
L. Wu, M. K. Hussain, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker, “Analog fault simulation automation at schematic level with random sampling techniques,” 2018, doi: 10.1109/DTIS.2018.8368549.
LibreCat
| Files available
| DOI
2018 | Book (Editor) | LibreCat-ID: 53595
O. Bringmann, W. Ecker, W. Müller, and D. Müller-Gridschneder, Eds., Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT. Dresden, Germany, 2018.
LibreCat
2017 | Conference Paper | LibreCat-ID: 24220
P. Adelt, B. Koppelmann, W. Müller, D. Mueller-Gritschneder, B. Kleinjohann, and C. Scheytt, “Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen,” 2017, doi: 10.17619/UNIPB/1-93.
LibreCat
| Files available
| DOI
2017 | Conference Paper | LibreCat-ID: 24223
L. Wu, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker, “SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study,” in 2nd Workshop on Resiliency in Embedded Electronic Systems (REES), 2017, p. 68.
LibreCat
| Files available
2017 | Conference Paper | LibreCat-ID: 24224
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and C. Scheytt, “ANALISA - A Tool for Static Instruction Set Analysis,” 2017.
LibreCat
| Files available
2017 | Conference Paper | LibreCat-ID: 24225
P. Adelt, B. Koppelmann, W. Müller, B. Kleinjohann, and C. Scheytt, “An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries,” in 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) , 2017, p. 44.
LibreCat
| Files available
2016 | Conference Paper | LibreCat-ID: 24264
P. Adelt, B. Koppelmann, W. Müller, M. Becker, B. Kleinjohann, and C. Scheytt, “Fast Dynamic Fault Injection for Virtual Microcontroller Platforms,” 2016, doi: 10.1109/VLSI-SoC.2016.7753545.
LibreCat
| Files available
| DOI
2016 | Conference Paper | LibreCat-ID: 24263
S. Abughannam, L. Wu, W. Müller, C. Scheytt, W. Ecker, and C. Novello, “Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study,” 2016.
LibreCat
| Files available
2015 | Conference Paper | LibreCat-ID: 24289
W. Müller, L. Wu, C. Scheytt, M. Becker, and S. Schoenberg, “On the Correlation of HW Faults and SW Errors,” in Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014), 2015.
LibreCat
2015 | Book (Editor) | LibreCat-ID: 53590
D. Müller-Gridschneder, W. Müller, and S. Mitra, Eds., Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems. Amsterdam, Netherlands, 2015.
LibreCat
2014 | Conference Paper | LibreCat-ID: 25145
M. Becker, C. Kuznik, and W. Müller, “Virtual Platforms for Model-Based Design of Dependable Cyber-Physical System Software,” 2014.
LibreCat
2014 | Conference Paper | LibreCat-ID: 25155
M. Becker, C. Kuznik, and W. Müller, “Fault Effect Modeling in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems,” 2014.
LibreCat
2014 | Conference Paper | LibreCat-ID: 25161
B. Koppelmann, M. Becker, and W. Müller, “Portierung der TriCore-Architektur auf QEMU,” 2014.
LibreCat
2014 | Conference Paper | LibreCat-ID: 24305
F. Mischkalla and W. Müller, “Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation,” 2014, doi: 10.1109/SAMOS.2014.6893219.
LibreCat
| Files available
| DOI
2014 | Journal Article | LibreCat-ID: 24302
B. Koppelmann, B. Messidat, M. Becker, C. Kuznik, W. Müller, and C. Scheytt, “Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” Design and Verification Conference (DVCON EUROPE), 2014.
LibreCat
| Files available
2014 | Journal Article | LibreCat-ID: 24309
C. Kuznik and W. Müller, “Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure,” Design, Automation and Test in Europe DATE, University Booth, Dresden, 2014.
LibreCat
| Files available
2014 | Conference Paper | LibreCat-ID: 24311
J.-H. Oetjens et al., “Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges,” 2014, doi: 10.1145/2593069.2602976.
LibreCat
| Files available
| DOI
2014 | Conference Paper | LibreCat-ID: 25120
F. Mischkalla and W. Müller, “Architectural Low-Power Design Using Transaction-Based System Simulation,” Greece, Sep. 2014, IEEE, 2014.
LibreCat
2014 | Conference Paper | LibreCat-ID: 25146
M. tech. M. M. Joy, W. Müller, and F.-J. Rammig, “Source code annotated memory leak detection for soft real time embedded systems with resource constraints,” 2014.
LibreCat
2014 | Conference Paper | LibreCat-ID: 25144
F. Mischkalla and W. Müller, “Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation,” 2014.
LibreCat
2014 | Conference Paper | LibreCat-ID: 36918
M. Becker, C. Kuznik, and W. Müller, “Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems,” presented at the ACM/IEEE International Conference on Cyber-Physical Systems (ICCPS), Berlin, 2014, doi: 10.1109/ICCPS.2014.6843726.
LibreCat
| DOI
2014 | Conference Paper | LibreCat-ID: 36917
C. Kuznik, W. Müller, and G. B. Defo, “An Assisted Single Source Verification Metric Model Code Generation Methodology,” presented at the Proceedings of the Electronic System Level Synthesis Conference (ESLSyn), 2014.
LibreCat
2014 | Conference Paper | LibreCat-ID: 25166
C. Kuznik and W. Müller, “Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM,” 2014.
LibreCat
2014 | Conference Paper | LibreCat-ID: 25163
C. Kuznik, B. G. Defo, and W. Müller, “Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung,” 2014.
LibreCat
2014 | Journal Article | LibreCat-ID: 25151
C. Kuznik, B. G. Defo, and W. Müller, “An Assisted Single Source Verification Metric Model Code Generation Methodology,” Electronic System Level Synthesis Conference (ESLSyn), 2014.
LibreCat
2014 | Conference Paper | LibreCat-ID: 34585
B. Koppelmann, B. Messidat, M. Becker, W. Müller, and J. C. Scheytt, “Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” 2014.
LibreCat
2014 | Journal Article | LibreCat-ID: 25164
M. Becker, W. Müller, J. Stroop, and U. Kiffmeier, “HeroeS - A Framework for Heterogeneous Software-Intensive System Design with SystemC,” Design, Automation and Test in Europe DATE, University Booth, Dresden, 2014.
LibreCat
2013 | Conference Paper | LibreCat-ID: 25270
M. tech. M. M. Joy, W. Müller, and F.-J. Rammig, “Early Phase Memory Leak Detection in Embedded Software Designs with Virtual Memory Management Model,” 2013.
LibreCat
2013 | Conference Paper | LibreCat-ID: 25271
D. He and W. Müller, “AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS,” 2013.
LibreCat
2013 | Conference Paper | LibreCat-ID: 25284
F. Mischkalla and W. Müller, “ Efficient Power Intent Validation Using Loosely-Timed Simulation Models,” 2013.
LibreCat
2013 | Conference Paper | LibreCat-ID: 25291
M. Becker, U. Kiffmeier, and W. Müller, “HeroeS: Virtual Platform Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time Architectures,” 2013.
LibreCat
2013 | Conference Paper | LibreCat-ID: 25606
C. Kuznik, M. F. S. Oliveira, and W. Müller, “SystemC Verification Components - An enhanced OVM/UVM for SystemC,” Mrz. 2013 - Poster, 2013.
LibreCat
2013 | Conference Paper | LibreCat-ID: 25612
F. Mischkalla and W. Müller, “Funktionale Verifikation von Low-Power Designs unter Verwendung Virtueller Prototypen,” 2013.
LibreCat
2013 | Conference Paper | LibreCat-ID: 25614
C. Kuznik, M. F. S. Oliveira, and W. Müller, “SC OVM: An Advanced SystemC Library for OVM-based Verification,” 2013.
LibreCat
2013 | Newspaper Article | LibreCat-ID: 25615
G. Engels, C. Gerth, L. Kleinjohann, B. Kleinjohann, and W. Müller, “ Informationstechnik spart Ressourcen,” ForschungsForum Paderborn , 2013.
LibreCat
2013 | Conference Paper | LibreCat-ID: 25620
C. Kuznik, M. F. Oliveira, B. Defo, and W. Müller, “Systematic Application of UCIS to Improve the Automation on Verification Closure,” 2013.
LibreCat
2013 | Conference Paper | LibreCat-ID: 25632
K. Klobedanz, J. Jatzkowski, A. Rettberg, and W. Müller, “Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks,” 2013.
LibreCat
2013 | Journal Article | LibreCat-ID: 25740
D. He and W. Müller, “ A heuristic energy-aware approach for hard real-time systems on multi-core platforms,” Microprocessors and Microsystems - Embedded Hardware Design 37(6-7), pp. 845–857, 2013.
LibreCat
2013 | Book Chapter | LibreCat-ID: 25743
H. Anacker et al., “Methods for the Design and Development,” in Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future, Heidelberg: Springer-Verlag, 2013, pp. 187–356.
LibreCat
2013 | Conference Paper | LibreCat-ID: 36919
F. Mischkalla and W. Müller, “Efficient Power-Intent Validation Using ‘Loosely-Timed’ Simulation Models: A Non-Invasive Approach,” presented at the 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2013, doi: 10.1109/PATMOS.2013.6662171.
LibreCat
| DOI
2013 | Conference Paper | LibreCat-ID: 36920
D. He and W. Müller, “An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors,” in Proceedings of the International Conference on Applied Computing (AC), 2013.
LibreCat
2012 | Conference Paper | LibreCat-ID: 25744
M. tech. M. M. Joy, M. Becker, E. Mathews, and W. Müller, “Automated Source Code Annotation for Timing Analysis of Embedded Software,” Bangalore, 14. - 16. Dez. 2012, IEEE, 2012.
LibreCat
2012 | Conference Paper | LibreCat-ID: 25758
M. Becker, D. Baldin, C. Kuznik, M. tech. M. M. Joy, T. Xie, and W. Müller, “XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software,” 2012.
LibreCat
2012 | Conference Paper | LibreCat-ID: 25761
M. F. Oliveira et al., “The System Verification Methodology for Advanced TLM Verification,” 2012.
LibreCat
2012 | Conference Paper | LibreCat-ID: 25767
D. He and W. Müller, “A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms,” 2012.
LibreCat
2012 | Conference Paper | LibreCat-ID: 26022
M. Becker, C. Kuznik, M. tech. M. M. Joy, T. Xie, and W. Müller, “Binary Mutation Testing Through Dynamic Translation,” 2012.
LibreCat
| Download (ext.)
2012 | Conference Paper | LibreCat-ID: 26023
D. He and W. Müller, “Enhanced Schedulability Analysis of Hard Real-Time Systems on Power Manageable Multi-Core Platforms,” 2012.
LibreCat
2012 | Conference Paper | LibreCat-ID: 26024
S. Radke et al., “Compilation of Methodologies to Speed up the Verification Process at System Level,” 2012.
LibreCat
| Download (ext.)
2012 | Conference Paper | LibreCat-ID: 26031
D. He and W. Müller, “Online Energy-Efficient Hard Real-Time Scheduling for Component Oriented Systems,” 2012.
LibreCat
2012 | Conference Paper | LibreCat-ID: 26036
M. F. Oliveira, C. Kuznik, W. Müller, W. Ecker, and V. Esen, “A SystemC Library for Advanced TLM Verification,” 2012.
LibreCat
2012 | Conference Paper | LibreCat-ID: 26079
M. Becker, G. B. Gnokam Defo, W. Müller, F. Fummi, G. Pravadelli, and S. Vinco, “MOUSSE: scaling MOdelling and verification to complex heterogeneoUS embedded Systems Evolution,” 2012.
LibreCat
2012 | Conference Paper | LibreCat-ID: 26080
M. Becker, C. Kuznik, M. tech. M. Joy, T. Xie, and W. Müller, “XEMU: A QEMU Based Binary Mutation Testing Framework,” 2012.
LibreCat
2012 | Conference Paper | LibreCat-ID: 26092
W. Müller, M. Becker, H. Zabel, A. Elfeky, and A. DiPasquale, “Virtual Prototyping of Cyber-Physical Systems,” 2012.
LibreCat
2012 | Book Chapter | LibreCat-ID: 26695
Y. Vanderperren, W. Müller, D. He, F. Mischkalla, and W. Dahaene, “Extending UML for Electronic Systems Design: A Code Generation Perspective,” in Design Technology for Heterogeneous Embedded Systems, 1st Edition. Auflage., G. Nicolescu, I. O’Connor, and C. Piguet, Eds. Springer Verlag, 2012, pp. 13–39.
LibreCat
2012 | Conference Paper | LibreCat-ID: 36922
K. Klobedanz, W. Müller, and A. Rettberg, “An Approach for Self-Reconfiguring and Fault-Tolerant Distributed Real-Time Systems,” presented at the IEEE 15th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2012, doi: 10.1109/ISORCW.2012.41.
LibreCat
| DOI
2012 | Conference Paper | LibreCat-ID: 36921
M. F. Oliveira, C. Kuznik, W. Müller, V. Esen, and W. Ecker, “Towards an Enhanced UVM for SystemC,” 2012.
LibreCat
2012 | Conference Paper | LibreCat-ID: 36994
T. Xie, W. Müller, and F. Letombe, “Mutation-Analysis Driven Functional Verification of a Soft Microprocessor,” 2012, doi: 10.1109/SOCC.2012.6398362.
LibreCat
| DOI
2012 | Conference Paper | LibreCat-ID: 36997
T. Xie and W. Müller, “An IP-XACT-TO-SystemC Model Generator for Mutation Analysis,” 2012.
LibreCat
2012 | Journal Article | LibreCat-ID: 26038
C. Kuznik, M. F. Oliveira, and W. Müller, “SYSTEMC UVM VERIFICATION COMPONENTS,” Design, Automation and Test in Europe DATE, 2012.
LibreCat
2012 | Book (Editor) | LibreCat-ID: 53593
W. Müller and W. Ecker, Eds., Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs . Tampere, Finland, 2012.
LibreCat
2011 | Conference Paper | LibreCat-ID: 26667
C. Kuznik and W. Müller, “Aspect enhanced functional coverage driven verification in the SystemC HDVL,” 2011.
LibreCat
2011 | Conference Paper | LibreCat-ID: 26669
T. Xie and W. Müller, “IP-XACT based System Level Mutation Testing,” 2011.
LibreCat
2011 | Conference Paper | LibreCat-ID: 26698
T. Xie and W. Müller, “HDL-Mutation Based Simulation Data Generation by Propagation Guided Search,” 2011.
LibreCat
2011 | Journal Article | LibreCat-ID: 26705
C. Kuznik and W. Müller, “Verification Closure of SystemC Designs with Functional Coverage,” North American SystemC User Group Meeting (16th), 2011.
LibreCat
2011 | Conference Paper | LibreCat-ID: 26710
M. Becker, H. Zabel, W. Müller, A. Elfeky, and A. DiPasquale, “Virtual Prototyping softwareintensiver mechatronischer Systeme Eine Fallstudie,” in 8. Paderborner Workshop Entwurf mechatronischer Systeme, Band 294, 2011, vol. 294, pp. 315–327.
LibreCat
2011 | Conference Paper | LibreCat-ID: 26713
K. Klobedanz, A. König, and W. Müller, “A Reconfiguration Approach for Fault-Tolerant FlexRay Networks,” 14. - 18. Mrz. 2011, 2011.
LibreCat
2011 | Conference Paper | LibreCat-ID: 26714
K. Klobedanz, A. König, W. Müller, and A. Rettberg, “Self-Reconfiguration for Fault-Tolerant FlexRay Networks,” 2011.
LibreCat
2011 | Conference Paper | LibreCat-ID: 26715
C. Kuznik and W. Müller, “Functional Coverage-driven Verification with SystemC on Multiple Level of Abstraction,” 2011.
LibreCat
2011 | Conference Paper | LibreCat-ID: 26716
F. Mischkalla, D. He, and W. Müller, “A Retargetable SysML-based Front-End for High-Level Synthesis,” 2011.
LibreCat
2011 | Conference Paper | LibreCat-ID: 26717
D. He, F. Mischkalla, and W. Müller, “A SysML-based Framework with QEMU-SystemC Code Generation,” 2011.
LibreCat
2011 | Conference Paper | LibreCat-ID: 26784
G. B. Gnokam Defo and W. Müller, “Synchronisation eines SystemC Restbus-Simulators mit einem Hardware-In-the-Loop FlexRay Netzwerk,” 2011.
LibreCat
2011 | Conference Paper | LibreCat-ID: 26789
C. Kuznik and W. Müller, “Native binary mutation analysis for embedded software and virtual prototypes in SystemC,” 2011.
LibreCat
2011 | Conference Paper | LibreCat-ID: 37001
M. Becker, H. Zabel, W. Müller, and A. Elfeky, “Virtual Prototyping software-intensiver mechatronischer Systeme - Eine Fallstudie,” presented at the 8. Paderborner Workshop Entwurf Mechatronischer Systeme, 2011.
LibreCat
2011 | Conference Paper | LibreCat-ID: 37005
C. Kuznik and W. Müller, “A SystemC Based Library for Functional Coverage,” presented at the Proceedings of the Design and Verification Conference (DVCON 2011), San Jose, CA, 2011.
LibreCat
2011 | Conference Paper | LibreCat-ID: 37006
K. Klobedanz, A. König, and W. Müller, “A Reconfiguration Approach for Faul-Tolerant FlexRay Networks,” presented at the 2011 Design, Automation & Test in Europe, Grenoble, France, 2011, doi: 10.1109/DATE.2011.5763022.
LibreCat
| DOI
2011 | Book (Editor) | LibreCat-ID: 53580
W. Müller and F. Petrot, Eds., Proceedings of the 1st International QEMU Users’ Forum. 2011.
LibreCat
2010 | Conference Paper | LibreCat-ID: 37007
F. Mischkalla, D. He, and W. Müller, “Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems,” presented at the 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden, 2010, doi: 10.1109/DATE.2010.5456990.
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 37009
M. F. S. Oliveira, H. Zabel, and W. Müller, “Assertion-Based Verification of RTOS Properties,” presented at the 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden, 2010, doi: 10.1109/DATE.2010.5457130.
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 37011
K. Klobedanz, C. Kuznik, A. Thuy, and W. Müller, “Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study,” presented at the 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden, 2010, doi: 10.1109/DATE.2010.5457125.
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 37037
A. Krupp and W. Müller, “A Systematic Approach to Combined HW/SW System Test,” presented at the Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden, 2010, doi: 10.1109/DATE.2010.5457186.
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 37040
M. Becker, G. Di Guglielmo, F. Fummi, W. Müller, G. Pravadelli, and T. Xie, “RTOS-Aware Refinement for TLM2.0-based HW/SW Design,” presented at the Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden, 2010, doi: 10.1109/DATE.2010.5456965.
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 37046
M. Becker, H. Zabel, and W. Müller, “A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement,” 2010, doi: 10.1007/978-3-642-15234-4_15.
LibreCat
| DOI
2010 | Conference Paper | LibreCat-ID: 37044
K. Klobedanz, G. B. Defo, H. Zabel, W. Müller, and Y. Zhi, “Task Migration for Fault-Tolerant FlexRay Networks,” 2010, doi: 10.1007/978-3-642-15234-4_7.
LibreCat
| DOI