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264 Publications
2024 | Conference Paper | LibreCat-ID: 45778
Luchterhandt, Lars, et al. “Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells.” MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, VDE Verlag, 2024.
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2024 | Conference Paper | LibreCat-ID: 53579
Palomero Bernardo, Paul, et al. “A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing.” DATE 24 - Design Automation and Test in Europe, 2024.
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2023 | Conference Paper | LibreCat-ID: 45775
Luchterhandt, Lars, et al. “Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture.” MBMV 2023 - 26. Workshop "Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg, VDE Verlag, 2023.
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2023 | Conference Paper | LibreCat-ID: 45776
Ecker, Wolfgang, et al. “Scale4Edge – Scaling RISC-V for Edge Applications.” RISC-V Summit Europe 2023, Barcelona, Spain, June 2023., 2023.
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2023 | Conference Paper | LibreCat-ID: 48530
Müller, Wolfgang, et al. “Der TETRISC SoC - Ein Resilientes Quad-Core System Auf Pulpissimo-Basis.” 5. ITG / GMM / GI -Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen , 2023.
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2023 | Conference Abstract | LibreCat-ID: 48961
Iftekhar, Mohammed, et al. “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 Nm FD-SOI CMOS Technology.” 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2023, doi:10.1109/BCICTS54660.2023.10310954.
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2022 | Conference Paper | LibreCat-ID: 29302
Ecker, Wolfgang, et al. “The Scale4Edge RISC-V Ecosystem.” In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022), 2022.
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2021 | Conference Paper | LibreCat-ID: 32125
Adelt, Peer, et al. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, 2021.
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2021 | Conference Paper | LibreCat-ID: 32132
Adelt, Peer, et al. “QEMU zur Simulation von Worst-Case-Ausführungszeiten.” MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, VDE, 2021.
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2021 | Conference Paper | LibreCat-ID: 23992
Adelt, Peer, et al. “Register and Instruction Coverage Analysis for Different RISC-V ISA Modules.” Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2021), 2021.
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2020 | Conference Paper | LibreCat-ID: 24027
Adelt, Peer, et al. “A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures.” MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop, 2020.
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2019 | Conference Paper | LibreCat-ID: 24058
Koppelmann, Bastian, et al. “RISC-V Extensions for Bit Manipulation Instructions.” 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2019, doi:10.1109/PATMOS.2019.8862170.
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2019 | Conference Paper | LibreCat-ID: 24060
Adelt, Peer, et al. “Analyse Sicherheitskritischer Software Für RISC-V Prozessoren.” MBMV 2019-22.Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2019), 2019.
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2019 | Conference Paper | LibreCat-ID: 24061
Adelt, Peer, et al. “QEMU for Dynamic Memory Analysis of Security Sensitive Software.” 2nd International Workshop on Embedded Software for Industrial IoT in Conjunction with DATE 2019, 2019, pp. 32–34.
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2019 | Journal Article | LibreCat-ID: 24063
Adelt, Peer, et al. “QEMU Support for RISC-V: Current State and Future Releases.” 2nd International Workshop on RISC-V Research Activities, vol. (Presentation), 2019.
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2019 | Book (Editor) | LibreCat-ID: 53596
Bringmann, Oliver, et al., editors. Proceedings of the 2nd International Workshop on Embedded Software for Industrial IoT - ESIIT. 2019.
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2018 | Journal Article | LibreCat-ID: 24194
Adelt, Peer, et al. “Current and Future RISC-V Activities for Virtual Prototyping and Chip Design.” International Workshop on RISC-V Research Activities, vol. Presentation, 2018.
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2018 | Conference Paper | LibreCat-ID: 24196
Wu, Liang, et al. “Analog Fault Simulation Automation at Schematic Level with Random Sampling Techniques.” 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)) , IEEE, 2018, doi:10.1109/DTIS.2018.8368549.
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2018 | Book (Editor) | LibreCat-ID: 53595
Bringmann, Oliver, et al., editors. Proceedings of the 1st International Workshop on Embedded Software for Industrial IoT - ESIIT. 2018.
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2017 | Conference Paper | LibreCat-ID: 24220
Adelt, Peer, et al. “Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen.” Tagungsband des Wissenschaftsforums Intelligente Technische Systeme, Verlagsschriftenreihe des Heinz Nixdorf Instituts, 2017, doi:10.17619/UNIPB/1-93.
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2017 | Conference Paper | LibreCat-ID: 24223
Wu, Liang, et al. “SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study.” 2nd Workshop on Resiliency in Embedded Electronic Systems (REES), 2017, p. 68.
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2017 | Conference Paper | LibreCat-ID: 24224
Adelt, Peer, et al. “ANALISA - A Tool for Static Instruction Set Analysis.” Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation, 2017.
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2017 | Conference Paper | LibreCat-ID: 24225
Adelt, Peer, et al. “An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries.” 2nd Workshop on Resiliency in Embedded Electronic Systems (REES) , 2017, p. 44.
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2016 | Conference Paper | LibreCat-ID: 24264
Adelt, Peer, et al. “Fast Dynamic Fault Injection for Virtual Microcontroller Platforms.” Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC), 2016, doi:10.1109/VLSI-SoC.2016.7753545.
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2016 | Conference Paper | LibreCat-ID: 24263
Abughannam, Saed, et al. “Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study.” Analog 2016 - VDE, 2016.
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2015 | Conference Paper | LibreCat-ID: 24289
Müller, Wolfgang, et al. “On the Correlation of HW Faults and SW Errors.” Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014), edited by Daniel Mueller-Gritschneder et al., 2015.
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2015 | Book (Editor) | LibreCat-ID: 53590
Müller-Gridschneder, Daniel, et al., editors. Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems. 2015.
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2014 | Conference Paper | LibreCat-ID: 25145
Becker, Markus, et al. “Virtual Platforms for Model-Based Design of Dependable Cyber-Physical System Software.” 17th Euromicro Conference on Digital Systems Design (DSD), 2014.
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2014 | Conference Paper | LibreCat-ID: 25155
Becker, Markus, et al. “Fault Effect Modeling in a Heterogeneous SystemC Virtual Platform Framework for Cyber-Physical Systems.” ACM/IEEE 5th International Conference on Cyber-Physical Systems, 2014.
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2014 | Conference Paper | LibreCat-ID: 25161
Koppelmann, Bastian, et al. “Portierung Der TriCore-Architektur Auf QEMU.” 17. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2014) , 2014.
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2014 | Conference Paper | LibreCat-ID: 24305
Mischkalla, Fabian, and Wolfgang Müller. “Architectural Low-Power Design Using Transaction-Based System Modeling and Simulation.” Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), IEEE, 2014, doi:10.1109/SAMOS.2014.6893219.
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2014 | Journal Article | LibreCat-ID: 24302
Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” Design and Verification Conference (DVCON EUROPE), 2014.
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2014 | Journal Article | LibreCat-ID: 24309
Kuznik, Christoph, and Wolfgang Müller. “Verific-MM: Systematized Verification Metrics Generation with UCIS for Improved Automation on Verification Closure.” Design, Automation and Test in Europe DATE, University Booth, Dresden, 2014.
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2014 | Conference Paper | LibreCat-ID: 24311
Oetjens, Jan-Hendrik, et al. “Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges.” Design Automation Conference (DAC), 2014, doi:10.1145/2593069.2602976.
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2014 | Conference Paper | LibreCat-ID: 25120
Mischkalla, Fabian, and Wolfgang Müller. “Architectural Low-Power Design Using Transaction-Based System Simulation.” Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), IEEE, 2014.
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2014 | Conference Paper | LibreCat-ID: 25146
Joy, M. tech. Mabel Mary, et al. “Source Code Annotated Memory Leak Detection for Soft Real Time Embedded Systems with Resource Constraints.” 12th IEEE International Conference on Embedded Computing, 2014.
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2014 | Conference Paper | LibreCat-ID: 25144
Mischkalla, Fabian, and Wolfgang Müller. “Advanced SoC Virtual Prototyping for System-Level Power Planning and Validation.” PATMOS 2014, 2014.
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2014 | Conference Paper | LibreCat-ID: 36918
Becker, Markus, et al. Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems. IEEE, 2014, doi:10.1109/ICCPS.2014.6843726.
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2014 | Conference Paper | LibreCat-ID: 36917
Kuznik, Christoph, et al. An Assisted Single Source Verification Metric Model Code Generation Methodology. 2014.
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2014 | Conference Paper | LibreCat-ID: 25166
Kuznik, Christoph, and Wolfgang Müller. “Modellierung effizienter Stresstest-Umgebungen für virtuelle Prototypen mit SVM.” 26. ITG / GI / GMM Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, 2014.
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2014 | Conference Paper | LibreCat-ID: 25163
Kuznik, Christoph, et al. “Semi-automatische Generierung von Überdeckungsmetriken mittels methodischer Verikationsplan Verarbeitung.” 17. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2014) , 2014.
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2014 | Journal Article | LibreCat-ID: 25151
Kuznik, Christoph, et al. “An Assisted Single Source Verification Metric Model Code Generation Methodology.” Electronic System Level Synthesis Conference (ESLSyn), 2014.
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2014 | Conference Paper | LibreCat-ID: 34585
Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based SoCs Using QEMU.” Proceedings of the Design and Verification Conference Europe (DVCON Europe), 2014.
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2014 | Journal Article | LibreCat-ID: 25164
Becker, Markus, et al. “HeroeS - A Framework for Heterogeneous Software-Intensive System Design with SystemC.” Design, Automation and Test in Europe DATE, University Booth, Dresden, 2014.
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2013 | Conference Paper | LibreCat-ID: 25270
Joy, M. tech. Mabel Mary, et al. “Early Phase Memory Leak Detection in Embedded Software Designs with Virtual Memory Management Model.” Proceedings of AVICPS 2013, Dez. 2013 IEEE Computer Society, Linköping University Electronic Press, 2013.
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2013 | Conference Paper | LibreCat-ID: 25271
He, Da, and Wolfgang Müller. “AN ENERGY-EFFICIENT HEURISTIC FOR HARD REAL- TIME SYSTEM ON MULTI-CORE PROCESSORS.” Proceedings of International Conference on Applied Computing (AC), 2013.
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2013 | Conference Paper | LibreCat-ID: 25284
Mischkalla, Fabian, and Wolfgang Müller. “ Efficient Power Intent Validation Using Loosely-Timed Simulation Models.” 23rd International Workshop on Power And Timing Modeling, Optimization and Simulation, Sep. 2013, 2013.
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2013 | Conference Paper | LibreCat-ID: 25291
Becker, Markus, et al. “HeroeS: Virtual Platform Driven Integration of Heterogeneous Software Components for Multi-Core Real-Time Architectures.” 16th IEEE Computer Society Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2013.
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2013 | Conference Paper | LibreCat-ID: 25606
Kuznik, Christoph, et al. “SystemC Verification Components - An Enhanced OVM/UVM for SystemC.” EdaWorkshop 13, 2013.
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2013 | Conference Paper | LibreCat-ID: 25612
Mischkalla, Fabian, and Wolfgang Müller. “Funktionale Verifikation von Low-Power Designs unter Verwendung Virtueller Prototypen.” Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013.
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2013 | Conference Paper | LibreCat-ID: 25614
Kuznik, Christoph, et al. “SC OVM: An Advanced SystemC Library for OVM-Based Verification.” Open SANITAS SystemC Verification Workshop, 2013.
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2013 | Newspaper Article | LibreCat-ID: 25615
Engels, Gregor, et al. “ Informationstechnik spart Ressourcen.” ForschungsForum Paderborn , 2013.
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2013 | Conference Paper | LibreCat-ID: 25620
Kuznik, Christoph, et al. “Systematic Application of UCIS to Improve the Automation on Verification Closure.” Proceedings of DVCON, 2013.
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2013 | Conference Paper | LibreCat-ID: 25632
Klobedanz, Kay, et al. “Fault-Tolerant Deployment of Real-Time Software in AUTOSAR ECU Networks.” International Embedded Systems Symposium (IESS) 2013, Springer, 2013.
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2013 | Journal Article | LibreCat-ID: 25740
He, Da, and Wolfgang Müller. “ A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms.” Microprocessors and Microsystems - Embedded Hardware Design 37(6-7), 2013, pp. 845–57.
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2013 | Book Chapter | LibreCat-ID: 25743
Anacker, Harald, et al. “Methods for the Design and Development.” Design Methodology for Intelligent Technical Systems Systems – Develop Intelligent Technical Systems of the Future, Springer-Verlag, 2013, pp. 187–356.
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2013 | Conference Paper | LibreCat-ID: 36919
Mischkalla, Fabian, and Wolfgang Müller. Efficient Power-Intent Validation Using “Loosely-Timed” Simulation Models: A Non-Invasive Approach. IEEE, 2013, doi:10.1109/PATMOS.2013.6662171.
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2013 | Conference Paper | LibreCat-ID: 36920
He, Da, and Wolfgang Müller. “An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors.” Proceedings of the International Conference on Applied Computing (AC), edited by Hans Weghorn, 2013.
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2012 | Conference Paper | LibreCat-ID: 25744
Joy, M. tech. Mabel Mary, et al. “Automated Source Code Annotation for Timing Analysis of Embedded Software.” In Proceedings of Advanced Computing and Communications Conference 2012 (ADCOM 2012), IEEE, 2012.
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2012 | Conference Paper | LibreCat-ID: 25758
Becker, Markus, et al. “XEMU: An Efficient QEMU Based Binary Mutation Testing Framework for Embedded Software.” EMSOFT’12: Teenth ACM International Conference on Embedded Software 2012 Proceedings , 2012.
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2012 | Conference Paper | LibreCat-ID: 25761
Oliveira, Marcio F., et al. “The System Verification Methodology for Advanced TLM Verification.” CODES/ISSS ’12: Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Proceedings, 2012.
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2012 | Conference Paper | LibreCat-ID: 25767
He, Da, and Wolfgang Müller. “A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-Core Platforms.” 15th Euromicro Conference on Digital System Design (DSD), IEEE Xplore, 2012.
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2012 | Conference Paper | LibreCat-ID: 26022
Becker, Markus, et al. “Binary Mutation Testing Through Dynamic Translation.” 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2012.
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2012 | Conference Paper | LibreCat-ID: 26023
He, Da, and Wolfgang Müller. “Enhanced Schedulability Analysis of Hard Real-Time Systems on Power Manageable Multi-Core Platforms.” Third International Symposium on Advances in Embedded Systems and Applications (ESA-2012), IEEE Xplore, 2012.
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2012 | Conference Paper | LibreCat-ID: 26024
Radke, Stephan, et al. “Compilation of Methodologies to Speed up the Verification Process at System Level.” EdaWorkshop 12, 2012.
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2012 | Conference Paper | LibreCat-ID: 26031
He, Da, and Wolfgang Müller. “Online Energy-Efficient Hard Real-Time Scheduling for Component Oriented Systems.” 2012 IEEE 15th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC), IEEE Xplore, 2012.
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2012 | Conference Paper | LibreCat-ID: 26036
Oliveira, Marcio F., et al. “A SystemC Library for Advanced TLM Verification.” Proceeding of Design and Verification Conference (DVCON), 2012.
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2012 | Conference Paper | LibreCat-ID: 26079
Becker, Markus, et al. “MOUSSE: Scaling MOdelling and Verification to Complex HeterogeneoUS Embedded Systems Evolution.” Design, Automation and Test in Europe (DATE 2012), 2012.
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2012 | Conference Paper | LibreCat-ID: 26080
Becker, Markus, et al. “XEMU: A QEMU Based Binary Mutation Testing Framework.” Design, Automation and Test in Europe DATE, 2012.
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2012 | Conference Paper | LibreCat-ID: 26092
Müller, Wolfgang, et al. “Virtual Prototyping of Cyber-Physical Systems.” In Proceedings of 17th Asia and South Pacific Design Automation Conference (ASP-DAC 2012, 2012.
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2012 | Book Chapter | LibreCat-ID: 26695
Vanderperren, Yves, et al. “Extending UML for Electronic Systems Design: A Code Generation Perspective.” Design Technology for Heterogeneous Embedded Systems, edited by Gabriela Nicolescu et al., 1st Edition. Auflage, Springer Verlag, 2012, pp. 13–39.
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2012 | Conference Paper | LibreCat-ID: 36922
Klobedanz, Kay, et al. An Approach for Self-Reconfiguring and Fault-Tolerant Distributed Real-Time Systems. IEEE, 2012, doi:10.1109/ISORCW.2012.41.
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2012 | Conference Paper | LibreCat-ID: 36921
Oliveira, M. F., et al. “Towards an Enhanced UVM for SystemC.” Proceedings of the Design & Verification Conference (DVCon), 2012.
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2012 | Conference Paper | LibreCat-ID: 36994
Xie, Tao, et al. “Mutation-Analysis Driven Functional Verification of a Soft Microprocessor.” Proceedings of SOCC2012, IEEE, 2012, doi:10.1109/SOCC.2012.6398362.
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2012 | Conference Paper | LibreCat-ID: 36997
Xie, Tao, and Wolfgang Müller. “An IP-XACT-TO-SystemC Model Generator for Mutation Analysis.” Proceedings of the MeCoES’12, 2012.
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2012 | Journal Article | LibreCat-ID: 26038
Kuznik, Christoph, et al. “SYSTEMC UVM VERIFICATION COMPONENTS.” Design, Automation and Test in Europe DATE, 2012.
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2012 | Book (Editor) | LibreCat-ID: 53593
Müller, Wolfgang, and Wolfgang Ecker, editors. Proceedings of the 1st Workshop on Metamodelling and Code Generation for Embedded Systems - MeCoEs . 2012.
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2011 | Conference Paper | LibreCat-ID: 26667
Kuznik, Christoph, and Wolfgang Müller. “Aspect Enhanced Functional Coverage Driven Verification in the SystemC HDVL.” Proc. of the 8th International SoC Design Conference 2011 (ISOCC 2011), 2011.
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2011 | Conference Paper | LibreCat-ID: 26669
Xie, Tao, and Wolfgang Müller. “IP-XACT Based System Level Mutation Testing.” Proceedings of the 16th IEEE International High Level Design Validation and Test Workshop (HLDVT), 2011.
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2011 | Conference Paper | LibreCat-ID: 26698
Xie, Tao, and Wolfgang Müller. “HDL-Mutation Based Simulation Data Generation by Propagation Guided Search.” Proceedings of the 14th Euromicro Conference on Digital System Design (DSD), 2011.
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2011 | Journal Article | LibreCat-ID: 26705
Kuznik, Christoph, and Wolfgang Müller. “Verification Closure of SystemC Designs with Functional Coverage.” North American SystemC User Group Meeting (16th), 2011.
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2011 | Conference Paper | LibreCat-ID: 26710
Becker, Markus, et al. “Virtual Prototyping Softwareintensiver Mechatronischer Systeme Eine Fallstudie.” 8. Paderborner Workshop Entwurf Mechatronischer Systeme, Band 294, vol. 294, Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2011, pp. 315–27.
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2011 | Conference Paper | LibreCat-ID: 26713
Klobedanz, Kay, et al. “A Reconfiguration Approach for Fault-Tolerant FlexRay Networks.” Proceedings of Design, Automation, Test Europe - DATE2011, IEEE Computer Society Press, 2011.
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2011 | Conference Paper | LibreCat-ID: 26714
Klobedanz, Kay, et al. “Self-Reconfiguration for Fault-Tolerant FlexRay Networks.” Second IEEE Workshop on Self-Organizing Real-Time Systems - SORT 2011, IEEE Computer Society Press, 2011.
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2011 | Conference Paper | LibreCat-ID: 26715
Kuznik, Christoph, and Wolfgang Müller. “Functional Coverage-Driven Verification with SystemC on Multiple Level of Abstraction.” Proceedings of DVCON , 2011.
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2011 | Conference Paper | LibreCat-ID: 26716
Mischkalla, Fabian, et al. “A Retargetable SysML-Based Front-End for High-Level Synthesis.” Proceedings of 2nd Workshop on Model Based Engineering for Embedded Systems Design (M-BED), 2011.
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2011 | Conference Paper | LibreCat-ID: 26717
He, Da, et al. “A SysML-Based Framework with QEMU-SystemC Code Generation.” Proceedings of 1st International QEMU Users Forum, 2011.
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2011 | Conference Paper | LibreCat-ID: 26784
Gnokam Defo, Gilles Bertrand, and Wolfgang Müller. “Synchronisation Eines SystemC Restbus-Simulators Mit Einem Hardware-In-the-Loop FlexRay Netzwerk.” Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV), 2011.
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2011 | Conference Paper | LibreCat-ID: 26789
Kuznik, Christoph, and Wolfgang Müller. “Native Binary Mutation Analysis for Embedded Software and Virtual Prototypes in SystemC.” Proceedings of the 17th IEEE Pacific Rim International Symposium on Dependable Computing, 2011.
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2011 | Conference Paper | LibreCat-ID: 37001
Becker, Markus, et al. Virtual Prototyping Software-Intensiver Mechatronischer Systeme - Eine Fallstudie. 2011.
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2011 | Conference Paper | LibreCat-ID: 37005
Kuznik, Christoph, and Wolfgang Müller. A SystemC Based Library for Functional Coverage. 2011.
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2011 | Conference Paper | LibreCat-ID: 37006
Klobedanz, Kay, et al. “A Reconfiguration Approach for Faul-Tolerant FlexRay Networks.” Proceedings of DATE’11, IEEE, 2011, doi:10.1109/DATE.2011.5763022.
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2011 | Book (Editor) | LibreCat-ID: 53580
Müller, Wolfgang, and Frederic Petrot, editors. Proceedings of the 1st International QEMU Users’ Forum. 2011.
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2010 | Conference Paper | LibreCat-ID: 37007
Mischkalla, Fabian, et al. “Closing the Gap between UML-Based Modeling and Simulation of Combined HW/SW Systems.” Proceedings of DATE’10, IEEE, 2010, doi:10.1109/DATE.2010.5456990.
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2010 | Conference Paper | LibreCat-ID: 37009
Oliveira, Marcio F. S., et al. “Assertion-Based Verification of RTOS Properties.” Proceedings of DATE’10, IEEE, 2010, doi:10.1109/DATE.2010.5457130.
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2010 | Conference Paper | LibreCat-ID: 37011
Klobedanz, Kay, et al. “Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study.” Proceedings of DATE’10, Dresden, IEEE, 2010, doi:10.1109/DATE.2010.5457125.
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2010 | Conference Paper | LibreCat-ID: 37037
Krupp, Alexander, and Wolfgang Müller. “A Systematic Approach to Combined HW/SW System Test.” Proceedings of DATE’10, IEEE, 2010, doi:10.1109/DATE.2010.5457186.
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2010 | Conference Paper | LibreCat-ID: 37040
Becker, Markus, et al. “RTOS-Aware Refinement for TLM2.0-Based HW/SW Design.” Proceedings of DATE’10, IEEE, 2010, doi:10.1109/DATE.2010.5456965.
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2010 | Conference Paper | LibreCat-ID: 37046
Becker, Markus, et al. A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement. Edited by L. Kleinjohann and B. Kleinjohann, Springer Verlag, 2010, doi:10.1007/978-3-642-15234-4_15.
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2010 | Conference Paper | LibreCat-ID: 37044
Klobedanz, Kay, et al. Task Migration for Fault-Tolerant FlexRay Networks. Edited by L. Kleinjohann and B. Kleinjohann, Springer Verlag, 2010, doi:10.1007/978-3-642-15234-4_7.
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