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165 Publications
1997 | Conference Paper | LibreCat-ID: 13009
Tsai K-H, Hellebrand S, Marek-Sadowska M, Rajski J. STARBIST: Scan Autocorrelated Random Pattern Generation. In: 34th ACM/IEEE Design Automation Conference (DAC’97). IEEE; 1997. doi:10.1109/dac.1997.597194
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1996 | Misc | LibreCat-ID: 13087
Hellebrand S, Wunderlich H-J. Using Embedded Processors for BIST. 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA; 1996.
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1996 | Misc | LibreCat-ID: 13088
Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. 2nd IEEE International On-Line Testing Workshop. Biarritz, France; 1996.
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1996 | Conference Paper | LibreCat-ID: 13010
Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. In: IEEE International Test Conference (ITC’96). IEEE; 1996:195-204. doi:10.1109/test.1996.556962
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1995 | Report | LibreCat-ID: 13026
Hellebrand S, Wunderlich H-J. Synthesis Procedures for Self-Testable Controllers. University of Siegen, Germany; 1995.
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1995 | Report | LibreCat-ID: 13027
Hellebrand S, Wunderlich H-J, Goncalves F, Paulo Teixeira J. Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. University Siegen, Germany; 1995.
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1995 | Report | LibreCat-ID: 13028
Hellebrand S, Herzog M, Wunderlich H-J. Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. University of Siegen, Germany; 1995.
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1995 | Misc | LibreCat-ID: 13086
Hellebrand S, Reeb B, Tarnick S, Wunderlich H-J. Pattern Generation for a Deterministic BIST Scheme. 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA; 1995.
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1995 | Journal Article | LibreCat-ID: 13011
Hellebrand S, Rajski J, Tarnick S, Venkataraman S, Courtois B. Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Transactions on Computers. 1995;44(2):223-233. doi:10.1109/12.364534
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1995 | Conference Paper | LibreCat-ID: 13012
Hellebrand S, Reeb B, Tarnick S, Wunderlich H-J. Pattern Generation for a Deterministic BIST Scheme. In: ACM/IEEE International Conference on Computer Aided Design (ICCAD’95). IEEE; 1995:88-94. doi:10.1109/iccad.1995.479997
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1994 | Report | LibreCat-ID: 13024
Hellebrand S, Juergensen A, Wunderlich H-J. Synthesis for Off-Line Testability. University of Siegen, Germany; 1994.
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1994 | Report | LibreCat-ID: 13025
Hellebrand S, Juergensen A, Stroele A, Wunderlich H-J. Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. University of Siegen, Germany; 1994.
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1994 | Misc | LibreCat-ID: 13083
Venkataraman S, Rajski J, Hellebrand S, Tarnick S. Effiziente Testsatzkodierung Für Prüfpfad-Basierte Selbsttestarchitekturen. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands; 1994.
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1994 | Misc | LibreCat-ID: 13084
Hellebrand S, Wunderlich H-J. Ein Verfahren Zur Testfreundlichen Steuerwerkssynthese. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands; 1994.
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1994 | Misc | LibreCat-ID: 13085
Hellebrand S, Paulo Teixeira J, Wunderlich H-J. Synthesis for Testability - the ARCHIMEDES Approach. 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA; 1994.
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1994 | Conference Paper | LibreCat-ID: 13014
Hellebrand S, Wunderlich H-J. An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures. In: ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94). IEEE; 1994:110-116. doi:10.1109/iccad.1994.629752
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1994 | Conference Paper | LibreCat-ID: 13059
Hellebrand S, Wunderlich H-J. Synthese schneller selbsttestbarer Steuerwerke. In: Tagungsband Der GI/GME/ITG-Fachtagung \& Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme. ; 1994:3-11.
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1994 | Conference Paper | LibreCat-ID: 13013
Hellebrand S, Wunderlich H-J. Synthesis of Self-Testable Controllers. In: European Design and Test Conference (EDAC/ETC/EUROASIC). ; 1994:580-585. doi:10.1109/edtc.1994.326815
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1993 | Misc | LibreCat-ID: 13081
Hellebrand S, Tarnick S, Rajski J, Courtois B. Effiziente Erzeugung Deterministischer Muster Im Selbsttest. 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany; 1993.
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1993 | Misc | LibreCat-ID: 13082
Hellebrand S, Wunderlich H-J. Synthesis of Self-Testable Controllers. ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France; 1993.
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