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136 Publications


1997 | Misc | LibreCat-ID: 13089
Tsai, K.-H., Hellebrand, S., Rajski, J., & Marek-Sadowska, M. (1997). STARBIST: Scan Autocorrelated Random Pattern Generation. 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA.
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1997 | Conference Paper | LibreCat-ID: 13009
Tsai, K.-H., Hellebrand, S., Marek-Sadowska, M., & Rajski, J. (1997). STARBIST: Scan Autocorrelated Random Pattern Generation. In {34th ACM/IEEE Design Automation Conference (DAC’97)}. Anaheim, CA, USA: {IEEE}. https://doi.org/10.1109/dac.1997.597194
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1996 | Misc | LibreCat-ID: 13087
Hellebrand, S., & Wunderlich, H.-J. (1996). Using Embedded Processors for BIST. 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA.
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1996 | Misc | LibreCat-ID: 13088
Hellebrand, S., Wunderlich, H.-J., & Hertwig, A. (1996). Mixed-Mode BIST Using Embedded Processors. 2nd IEEE International On-Line Testing Workshop. Biarritz, France.
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1996 | Conference Paper | LibreCat-ID: 13010
Hellebrand, S., Wunderlich, H.-J., & Hertwig, A. (1996). Mixed-Mode BIST Using Embedded Processors. In {IEEE International Test Conference (ITC’96)} (pp. 195–204). Washington, DC, USA: {IEEE}. https://doi.org/10.1109/test.1996.556962
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1995 | Report | LibreCat-ID: 13026
Hellebrand, S., & Wunderlich, H.-J. (1995). Synthesis Procedures for Self-Testable Controllers. University of Siegen, Germany.
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1995 | Report | LibreCat-ID: 13027
Hellebrand, S., Wunderlich, H.-J., Goncalves, F., & Paulo Teixeira, J. (1995). Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. University Siegen, Germany.
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1995 | Journal Article | LibreCat-ID: 13011
Hellebrand, S., Rajski, J., Tarnick, S., Venkataraman, S., & Courtois, B. (1995). Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. {IEEE Transactions on Computers}, 44(2), 223–233. https://doi.org/10.1109/12.364534
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1995 | Report | LibreCat-ID: 13028
Hellebrand, S., Herzog, M., & Wunderlich, H.-J. (1995). Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. University of Siegen, Germany.
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1995 | Conference Paper | LibreCat-ID: 13012
Hellebrand, S., Reeb, B., Tarnick, S., & Wunderlich, H.-J. (1995). Pattern Generation for a Deterministic BIST Scheme. In {ACM/IEEE International Conference on Computer Aided Design (ICCAD’95)} (pp. 88–94). San Jose, CA, USA: {IEEE (Comput. Soc. Press)}. https://doi.org/10.1109/iccad.1995.479997
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1995 | Misc | LibreCat-ID: 13086
Hellebrand, S., Reeb, B., Tarnick, S., & Wunderlich, H.-J. (1995). Pattern Generation for a Deterministic BIST Scheme. 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA.
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1994 | Conference Paper | LibreCat-ID: 13013
Hellebrand, S., & Wunderlich, H.-J. (1994). Synthesis of Self-Testable Controllers. In {European Design and Test Conference (EDAC/ETC/EUROASIC)} (pp. 580–585). Paris, France: {IEEE (Comput. Soc. Press)}. https://doi.org/10.1109/edtc.1994.326815
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1994 | Report | LibreCat-ID: 13025
Hellebrand, S., Juergensen, A., Stroele, A., & Wunderlich, H.-J. (1994). Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. University of Siegen, Germany.
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1994 | Conference Paper | LibreCat-ID: 13014
Hellebrand, S., & Wunderlich, H.-J. (1994). An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures. In {ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94)} (pp. 110–116). San Jose, CA, USA: {IEEE}. https://doi.org/10.1109/iccad.1994.629752
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1994 | Misc | LibreCat-ID: 13083
Venkataraman, S., Rajski, J., Hellebrand, S., & Tarnick, S. (1994). Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands.
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1994 | Misc | LibreCat-ID: 13084
Hellebrand, S., & Wunderlich, H.-J. (1994). Ein Verfahren zur testfreundlichen Steuerwerkssynthese. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands.
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1994 | Conference Paper | LibreCat-ID: 13059
Hellebrand, S., & Wunderlich, H.-J. (1994). Synthese schneller selbsttestbarer Steuerwerke. In {Tagungsband der GI/GME/ITG-Fachtagung \& Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme} (pp. 3–11). Oberwiesenthal, Informatik Xpress 4, TU Chemnitz Zwickau, Germany.
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1994 | Misc | LibreCat-ID: 13085
Hellebrand, S., Paulo Teixeira, J., & Wunderlich, H.-J. (1994). Synthesis for Testability - the ARCHIMEDES Approach. 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA.
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1994 | Report | LibreCat-ID: 13024
Hellebrand, S., Juergensen, A., & Wunderlich, H.-J. (1994). Synthesis for Off-line Testability. University of Siegen, Germany.
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1993 | Misc | LibreCat-ID: 13082
Hellebrand, S., & Wunderlich, H.-J. (1993). Synthesis of Self-Testable Controllers. ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France.
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