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165 Publications


2024 | Conference Paper | LibreCat-ID: 52744
Jafarzadeh, H., Klemme, F., Amrouch, H., Hellebrand, S., & Wunderlich, H.-J. (n.d.). Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. European Test Symposium, The Hague, Netherlands, May 20-24, 2024, 6.
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2024 | Conference Paper | LibreCat-ID: 52742
Jafarzadeh, H., Klemme, F., Amrouch, H., Hellebrand, S., & Wunderlich, H.-J. (n.d.). Vmin Testing under Variations: Defect vs. Fault Coverage. IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, 6.
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2024 | Conference Paper | LibreCat-ID: 52743
Hellebrand, S., Sadeghi-Kohan, S., & Wunderlich, H.-J. (n.d.). Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle. International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1.
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2024 | Conference Paper | LibreCat-ID: 52745
Wunderlich, H.-J., Jafarzadeh, H., & Hellebrand, S. (n.d.). Robust Test of Small Delay Faults under  PVT-Variations. International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1.
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2024 | Misc | LibreCat-ID: 50284
Stiballe, A., Reimer, J. D., Sadeghi-Kohan, S., & Hellebrand, S. (2024). Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024.
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2023 | Misc | LibreCat-ID: 35204
Ghazal, A., Sadeghi-Kohan, S., Reimer, J. D., & Hellebrand, S. (2023). On Cryptography Effects on Interconnect Reliability. 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023.
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2023 | Dissertation | LibreCat-ID: 46482 | OA
Sprenger, A. (2023). Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen. Universität Paderborn. https://doi.org/10.17619/UNIPB/1-1787
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2023 | Conference Paper | LibreCat-ID: 46739
Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2023). Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W). https://doi.org/10.1109/dsn-w58399.2023.00056
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2023 | Conference Paper | LibreCat-ID: 46738
Sadeghi-Kohan, S., Reimer, J. D., Hellebrand, S., & Wunderlich, H.-J. (2023). Optimizing the Streaming of Sensor Data with Approximate Communication. IEEE Asian Test Symposium (ATS’23), October 2023. IEEE Asian Test Symposium (ATS’23).
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2023 | Journal Article | LibreCat-ID: 46264
Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2023). Workload-Aware Periodic Interconnect BIST. IEEE Design &Test, 1–1. https://doi.org/10.1109/mdat.2023.3298849
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2023 | Conference Paper | LibreCat-ID: 45830
Jafarzadeh, H., Klemme, F., Reimer, J. D., Najafi Haghi, Z. P., Amrouch, H., Hellebrand, S., & Wunderlich, H.-J. (2023). Robust Pattern Generation for Small Delay Faults under Process Variations. IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023. IEEE International Test Conference (ITC’23), Anaheim, USA.
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2022 | Journal Article | LibreCat-ID: 29351
Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2022). Stress-Aware Periodic Test of Interconnects. Journal of Electronic Testing. https://doi.org/10.1007/s10836-021-05979-5
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2022 | Misc | LibreCat-ID: 29890
Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2022). EM-Aware Interconnect BIST. European Workshop on Silicon Lifecycle Management, March 18, 2022.
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2020 | Conference Paper | LibreCat-ID: 19422
Sprenger, A., Sadeghi-Kohan, S., Reimer, J. D., & Hellebrand, S. (2020). Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020.
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2020 | Misc | LibreCat-ID: 15419
Sadeghi-Kohan, S., & Hellebrand, S. (2020). Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020.
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2020 | Conference Paper | LibreCat-ID: 29200
Sadeghi-Kohan, S., & Hellebrand, S. (2020). Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 38th IEEE VLSI Test Symposium (VTS). https://doi.org/10.1109/vts48691.2020.9107591
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2020 | Conference Paper | LibreCat-ID: 19421
Holst, S., Kampmann, M., Sprenger, A., Reimer, J. D., Hellebrand, S., Wunderlich, H.-J., & Weng, X. (2020). Logic Fault Diagnosis of Hidden Delay Defects. IEEE International Test Conference (ITC’20), November 2020.
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2019 | Misc | LibreCat-ID: 8112
Maaz, M. U., Sprenger, A., & Hellebrand, S. (2019). A Hybrid Space Compactor for Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19).
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2019 | Journal Article | LibreCat-ID: 8667
Sprenger, A., & Hellebrand, S. (2019). Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. Journal of Circuits, Systems and Computers, 28(1), 1–23. https://doi.org/10.1142/s0218126619400012
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2019 | Journal Article | LibreCat-ID: 13048
Kampmann, M., A. Kochte, M., Liu, C., Schneider, E., Hellebrand, S., & Wunderlich, H.-J. (2019). Built-in Test for Hidden Delay Faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 38(10), 1956–1968.
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