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84 Publications


2004 | Conference Paper | LibreCat-ID: 13001
Wuertenberger A, S. Tautermann C, Hellebrand S. Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. In: IEEE International Test Conference (ITC’04). IEEE; 2004:926-935. doi:10.1109/test.2004.1387357
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2003 | Conference Paper | LibreCat-ID: 13002
Wuertenberger A, S. Tautermann C, Hellebrand S. A Hybrid Coding Strategy for Optimized Test Data Compression. In: IEEE International Test Conference (ITC’03). IEEE; 2003:451-459. doi:10.1109/test.2003.1270870
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2001 | Conference Paper | LibreCat-ID: 13004
Liang H-G, Hellebrand S, Wunderlich H-J. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. In: IEEE International Test Conference (ITC’01). IEEE; 2001:894-902. doi:10.1109/test.2001.966712
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2000 | Conference Paper | LibreCat-ID: 13005
Hellebrand S, Liang H-G, Wunderlich H-J. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. In: IEEE International Test Conference (ITC’00). IEEE; 2000:778-784. doi:10.1109/test.2000.894274
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1999 | Conference Paper | LibreCat-ID: 13006
Hellebrand S, Wunderlich H-J, A. Ivaniuk A, V. Klimets Y, N. Yarmolik V. Error Detecting Refreshment for Embedded DRAMs. In: 17th IEEE VLSI Test Symposium (VTS’99). IEEE; 1999:384-390. doi:10.1109/vtest.1999.766693
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1999 | Conference Paper | LibreCat-ID: 13066
N. Yarmolik V, V. Bykov I, Hellebrand S, Wunderlich H-J. Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. In: Third European Dependable Computing Conference (EDCC-3). ; 1999.
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1999 | Conference Paper | LibreCat-ID: 13067
Hellebrand S, Wunderlich H-J, N. Yarmolik V. Symmetric Transparent BIST for RAMs. In: Design Automation and Test in Europe (DATE’99). ; 1999:702-707.
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1998 | Conference Paper | LibreCat-ID: 13007
Hertwig A, Hellebrand S, Wunderlich H-J. Fast Self-Recovering Controllers. In: 16th IEEE VLSI Test Symposium (VTS’98). IEEE; 1998:296-302. doi:10.1109/vtest.1998.670883
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1998 | Conference Paper | LibreCat-ID: 13008
Hellebrand S, Wunderlich H-J, N. Yarmolik V. Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. In: Design Automation and Test in Europe (DATE’98). ; 1998:173-179. doi:10.1109/date.1998.655853
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1998 | Conference Paper | LibreCat-ID: 13063
N. Yarmolik V, V. Klimets Y, Hellebrand S, Wunderlich H-J. New Transparent RAM BIST Based on Self-Adjusting Output Data Compression. In: Design & Diagnostics of Electronic Circuits & Systems (DDECS’98). ; 1998:27-33.
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1997 | Conference Paper | LibreCat-ID: 13009
Tsai K-H, Hellebrand S, Marek-Sadowska M, Rajski J. STARBIST: Scan Autocorrelated Random Pattern Generation. In: 34th ACM/IEEE Design Automation Conference (DAC’97). IEEE; 1997. doi:10.1109/dac.1997.597194
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1996 | Conference Paper | LibreCat-ID: 13010
Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. In: IEEE International Test Conference (ITC’96). IEEE; 1996:195-204. doi:10.1109/test.1996.556962
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1995 | Conference Paper | LibreCat-ID: 13012
Hellebrand S, Reeb B, Tarnick S, Wunderlich H-J. Pattern Generation for a Deterministic BIST Scheme. In: ACM/IEEE International Conference on Computer Aided Design (ICCAD’95). IEEE; 1995:88-94. doi:10.1109/iccad.1995.479997
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1994 | Conference Paper | LibreCat-ID: 13014
Hellebrand S, Wunderlich H-J. An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures. In: ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94). IEEE; 1994:110-116. doi:10.1109/iccad.1994.629752
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1994 | Conference Paper | LibreCat-ID: 13059
Hellebrand S, Wunderlich H-J. Synthese schneller selbsttestbarer Steuerwerke. In: Tagungsband Der GI/GME/ITG-Fachtagung \& Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme. ; 1994:3-11.
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1994 | Conference Paper | LibreCat-ID: 13013
Hellebrand S, Wunderlich H-J. Synthesis of Self-Testable Controllers. In: European Design and Test Conference (EDAC/ETC/EUROASIC). ; 1994:580-585. doi:10.1109/edtc.1994.326815
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1993 | Conference Paper | LibreCat-ID: 13015
Venkataraman S, Rajski J, Hellebrand S, Tarnick S. An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers. In: ACM/IEEE International Conference on Computer Aided Design (ICCAD’93). IEEE; 1993. doi:10.1109/iccad.1993.580117
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1992 | Conference Paper | LibreCat-ID: 13016
Hellebrand S, Tarnick S, Rajski J, Courtois B. Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. In: IEEE International Test Conference (ITC’92). IEEE; 1992:120-129. doi:10.1109/test.1992.527812
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1990 | Conference Paper | LibreCat-ID: 13018
Hellebrand S, Wunderlich H-J. Tools and Devices Supporting the Pseudo-Exhaustive Test. In: European Design Automation Conference (EDAC’90). IEEE; 1990:13-17. doi:10.1109/edac.1990.136612
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1990 | Conference Paper | LibreCat-ID: 13019
Hellebrand S, Wunderlich H-J, F. Haberl O. Generating Pseudo-Exhaustive Vectors for External Testing. In: IEEE International Test Conference (ITC’90). IEEE; 1990:670-679. doi:10.1109/test.1990.114082
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