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138 Publications


2007 | Misc | LibreCat-ID: 13042
Oehler, P., Hellebrand, S., & Wunderlich, H.-J. (2007). An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany.
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2007 | Journal Article | LibreCat-ID: 13036
Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., & Straube, B. (2007). Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. {Informacije MIDEM, Ljubljana (Invited Paper)}, 37(4 (124)), 212–219.
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2007 | Misc | LibreCat-ID: 13043
Hellebrand, S. (2007). Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany.
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2006 | Journal Article | LibreCat-ID: 13045
Becker, B., Polian, I., Hellebrand, S., Straube, B., & Wunderlich, H.-J. (2006). DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme. {it -Information Technology}, 48(5), 305–311.
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2005 | Misc | LibreCat-ID: 13102
Oehler, P., & Hellebrand, S. (2005). Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria.
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2005 | Misc | LibreCat-ID: 13046
Oehler, P., & Hellebrand, S. (2005). A Low Power Design for Embedded DRAMs with Online Consistency Checking. Kleinheubachertagung 2005, Miltenberg, Germany.
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2005 | Conference Paper | LibreCat-ID: 12998
Ali, M., Welzl, M., & Hellebrand, S. (2005). A Dynamic Routing Mechanism for Network on Chip. In {23rd IEEE NORCHIP Conference} (pp. 70–73). Oulu, Finland: {IEEE}. https://doi.org/10.1109/norchp.2005.1596991
LibreCat | DOI
 

2005 | Conference Paper | LibreCat-ID: 12999
Ali, M., Welzl, M., Zwicknagl, M., & Hellebrand, S. (2005). Considerations for Fault-Tolerant Networks on Chips. In {IEEE International Conference on Microelectronics (ICM’05)}. Islamabad, Pakistan: {IEEE}. https://doi.org/10.1109/icm.2005.1590063
LibreCat | DOI
 

2005 | Conference Paper | LibreCat-ID: 13000
Oehler, P., & Hellebrand, S. (2005). Low Power Embedded DRAMs with High Quality Error Correcting Capabilities. In {10th IEEE European Test Symposium (ETS’05)} (pp. 148–153). Tallinn, Estonia: {IEEE}. https://doi.org/10.1109/ets.2005.28
LibreCat | DOI
 

2005 | Misc | LibreCat-ID: 13101
Ali, M., Welzl, M., & Hellebrand, S. (2005). Dynamic Routing: A Prerequisite for Reliable NoCs. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria.
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