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138 Publications


2007 | Misc | LibreCat-ID: 13042
Oehler, P., Hellebrand, S., & Wunderlich, H.-J. (2007). An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany.
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2007 | Journal Article | LibreCat-ID: 13036
Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., & Straube, B. (2007). Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. {Informacije MIDEM, Ljubljana (Invited Paper)}, 37(4 (124)), 212–219.
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2007 | Misc | LibreCat-ID: 13043
Hellebrand, S. (2007). Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany.
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2006 | Journal Article | LibreCat-ID: 13045
Becker, B., Polian, I., Hellebrand, S., Straube, B., & Wunderlich, H.-J. (2006). DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme. {it -Information Technology}, 48(5), 305–311.
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2005 | Misc | LibreCat-ID: 13102
Oehler, P., & Hellebrand, S. (2005). Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria.
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2005 | Misc | LibreCat-ID: 13046
Oehler, P., & Hellebrand, S. (2005). A Low Power Design for Embedded DRAMs with Online Consistency Checking. Kleinheubachertagung 2005, Miltenberg, Germany.
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2005 | Conference Paper | LibreCat-ID: 12998
Ali, M., Welzl, M., & Hellebrand, S. (2005). A Dynamic Routing Mechanism for Network on Chip. In {23rd IEEE NORCHIP Conference} (pp. 70–73). Oulu, Finland: {IEEE}. https://doi.org/10.1109/norchp.2005.1596991
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2005 | Conference Paper | LibreCat-ID: 12999
Ali, M., Welzl, M., Zwicknagl, M., & Hellebrand, S. (2005). Considerations for Fault-Tolerant Networks on Chips. In {IEEE International Conference on Microelectronics (ICM’05)}. Islamabad, Pakistan: {IEEE}. https://doi.org/10.1109/icm.2005.1590063
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2005 | Conference Paper | LibreCat-ID: 13000
Oehler, P., & Hellebrand, S. (2005). Low Power Embedded DRAMs with High Quality Error Correcting Capabilities. In {10th IEEE European Test Symposium (ETS’05)} (pp. 148–153). Tallinn, Estonia: {IEEE}. https://doi.org/10.1109/ets.2005.28
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2005 | Misc | LibreCat-ID: 13101
Ali, M., Welzl, M., & Hellebrand, S. (2005). Dynamic Routing: A Prerequisite for Reliable NoCs. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria.
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2004 | Conference Paper | LibreCat-ID: 13001
Wuertenberger, A., S. Tautermann, C., & Hellebrand, S. (2004). Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. In {IEEE International Test Conference (ITC’04)} (pp. 926–935). Charlotte, NC, USA: {IEEE}. https://doi.org/10.1109/test.2004.1387357
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2004 | Misc | LibreCat-ID: 13099
Breu, R., Fahringer, T., Fensel, D., Hellebrand, S., Middeldorp, A., & Scherzer, O. (2004). Im Westen viel Neues - Informatik an der Universität Innsbruck. OCG Journal, pp. 28-29.
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2004 | Conference Paper | LibreCat-ID: 13071
Liu Jing, M., Ruehrup, S., Schindelhauer, C., Volbert, K., Dierkes, M., Bellgardt, A., … Hilleringmann, U. (2004). Sensor Networks with More Features Using Less Hardware. In {GOR/NGB Conference Tilburg 2004}. Tilburg, Netherlands.
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2004 | Misc | LibreCat-ID: 13100
Hellebrand, S., Wuertenberger, A., & S. Tautermann, C. (2004). Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. 9th IEEE European Test Symposium, Ajaccio, Corsica, France.
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2003 | Conference Paper | LibreCat-ID: 13002
Wuertenberger, A., S. Tautermann, C., & Hellebrand, S. (2003). A Hybrid Coding Strategy for Optimized Test Data Compression. In {IEEE International Test Conference (ITC’03)} (pp. 451–459). Charlotte, NC, USA: {IEEE}. https://doi.org/10.1109/test.2003.1270870
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2003 | Misc | LibreCat-ID: 13098
Breu, R., Hellebrand, S., & Welzl, M. (2003). Experiences from Teaching Software Development in a Java Environment. Handouts ACS/IEEE Workshop on Practice and Experience with Java in Education, Tunis, Tunisia.
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2002 | Journal Article | LibreCat-ID: 13070
Liang, H., Hellebrand, S., & Wunderlich, H.-J. (2002). A Mixed-Mode BIST Scheme Based on Folding Compression. {Journal on Computer Science and Technology}, 17(2), 203–212.
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2002 | Journal Article | LibreCat-ID: 13069
Hellebrand, S., Liang, H.-G., & Wunderlich, H.-J. (2002). Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. {Journal of Electronic Testing - Theory and Applications (JETTA)}, 18(2), 157–168.
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2002 | Journal Article | LibreCat-ID: 13003
Hellebrand, S., Wunderlich, H.-J., A. Ivaniuk, A., V. Klimets, Y., & N. Yarmolik, V. (2002). Efficient Online and Offline Testing of Embedded DRAMs. {IEEE Transactions on Computers}, 51(7), 801–809. https://doi.org/10.1109/tc.2002.1017700
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2002 | Misc | LibreCat-ID: 13097
Hellebrand, S., & Wuertenberger, A. (2002). Alternating Run-Length Coding: A Technique for Improved Test Data Compression. IEEE International Workshop on Test Resource Partitioning, Baltimore, MD, USA.
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2001 | Journal Article | LibreCat-ID: 13068
Hellebrand, S., Liang, H.-G., & Wunderlich, H.-J. (2001). A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. {Journal of Electronic Testing - Theory and Applications (JETTA)}, 17(3/4), 341–349.
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2001 | Misc | LibreCat-ID: 13096
Liang, H.-G., Hellebrand, S., & Wunderlich, H.-J. (2001). Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. IEEE European Test Workshop, Stockholm, Sweden.
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2001 | Conference Paper | LibreCat-ID: 13004
Liang, H.-G., Hellebrand, S., & Wunderlich, H.-J. (2001). Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. In {IEEE International Test Conference (ITC’01)} (pp. 894–902). Baltimore, MD, USA: {IEEE}. https://doi.org/10.1109/test.2001.966712
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2001 | Journal Article | LibreCat-ID: 13047
Liang, H.-G., Hellebrand, S., & Wunderlich, H.-J. (2001). Deterministic BIST Scheme Based on Reseeding of Folding Counters. {Journal of Computer Research and Development, (Jisuanji Yanjiu Yu Fazhan)}, 38(8), 931.
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2000 | Misc | LibreCat-ID: 13094
Hellebrand, S., & Wunderlich, H.-J. (2000). Hardwarepraktikum im Diplomstudiengang Informatik. Handbuch Lehre, Berlin, Raabe Verlag.
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2000 | Misc | LibreCat-ID: 13095
Hellebrand, S., Liang, H.-G., & Wunderlich, H.-J. (2000). A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. IEEE European Test Workshop, Cascais, Portugal.
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2000 | Conference Paper | LibreCat-ID: 13005
Hellebrand, S., Liang, H.-G., & Wunderlich, H.-J. (2000). A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. In {IEEE International Test Conference (ITC’00)} (pp. 778–784). Atlantic City, NJ, USA: {IEEE}. https://doi.org/10.1109/test.2000.894274
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1999 | Conference Paper | LibreCat-ID: 13006
Hellebrand, S., Wunderlich, H.-J., A. Ivaniuk, A., V. Klimets, Y., & N. Yarmolik, V. (1999). Error Detecting Refreshment for Embedded DRAMs. In {17th IEEE VLSI Test Symposium (VTS’99)} (pp. 384–390). Dana Point, CA, USA: {IEEE (Comput. Soc.)}. https://doi.org/10.1109/vtest.1999.766693
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1999 | Book | LibreCat-ID: 13065
Hellebrand, S. (1999). Selbsttestbare Steuerwerke - Strukturen und Syntheseverfahren. Verlag Dr. Kovac, Hamburg: Verlag Dr. Kovac, Hamburg.
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1999 | Conference Paper | LibreCat-ID: 13066
N. Yarmolik, V., V. Bykov, I., Hellebrand, S., & Wunderlich, H.-J. (1999). Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. In {Third European Dependable Computing Conference (EDCC-3)}. Prague, Czech Republic.
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1999 | Conference Paper | LibreCat-ID: 13067
Hellebrand, S., Wunderlich, H.-J., & N. Yarmolik, V. (1999). Symmetric Transparent BIST for RAMs. In {Design, Automation and Test in Europe (DATE’99)} (pp. 702–707). Munich, Germany.
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1999 | Misc | LibreCat-ID: 13093
Hellebrand, S., Wunderlich, H.-J., & N. Yarmolik, V. (1999). Exploiting Symmetries to Speed Up Transparent BIST. 11th GI/ITG/GMM/IEEE Workshop.
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1998 | Conference Paper | LibreCat-ID: 13063
N. Yarmolik, V., V. Klimets, Y., Hellebrand, S., & Wunderlich, H.-J. (1998). New Transparent RAM BIST Based on Self-Adjusting Output Data Compression. In {Design \& Diagnostics of Electronic Circuits \& Systems} (pp. 27–33). Szczyrk, Poland.
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1998 | Conference Paper | LibreCat-ID: 13007
Hertwig, A., Hellebrand, S., & Wunderlich, H.-J. (1998). Fast Self-Recovering Controllers. In {16th IEEE VLSI Test Symposium (VTS’98)} (pp. 296–302). Monterey, CA, USA: {IEEE (Comput. Soc.)}. https://doi.org/10.1109/vtest.1998.670883
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1998 | Journal Article | LibreCat-ID: 13064
Hellebrand, S., Hertwig, A., & Wunderlich, H.-J. (1998). Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. {IEEE Design and Test}, 15(4), 36–41.
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1998 | Book Chapter | LibreCat-ID: 13060
Hellebrand, S., Wunderlich, H.-J., & Hertwig, A. (1998). Mixed-Mode BIST Using Embedded Processors. In Mixed-Mode BIST Using Embedded Processors. In: M. Nicolaidis, Y. Zorian, D. K. Pradhan (Eds.): On-Line Testing for VLSI, Boston: Kluwer Academic Publishers 1998: {Kluwer Academic Publishers}.
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1998 | Misc | LibreCat-ID: 13091
N. Yarmolik, V., Hellebrand, S., & Wunderlich, H.-J. (1998). Efficient Consistency Checking for Embedded Memories. 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA.
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1998 | Conference Paper | LibreCat-ID: 13008
Hellebrand, S., Wunderlich, H.-J., & N. Yarmolik, V. (1998). Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. In {IEEE Design, Automation and Test in Europe (DATE’98)} (pp. 173–179). Paris, France: {IEEE (Comput.Soc)}. https://doi.org/10.1109/date.1998.655853
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1998 | Journal Article | LibreCat-ID: 13061
Hellebrand, S., Wunderlich, H.-J., & Hertwig, A. (1998). Mixed-Mode BIST Using Embedded Processors. {Journal of Electronic Testing Theory and Applications - JETTA}, 12(1/2), 127–138.
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1998 | Misc | LibreCat-ID: 13092
N. Yarmolik, V., Hellebrand, S., & Wunderlich, H.-J. (1998). Efficient Consistency Checking for Embedded Memories. 10th GI/ITG/GMM/IEEE Workshop.
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1998 | Report | LibreCat-ID: 13029
Hellebrand, S., & Wunderlich, H.-J. (1998). Test und Synthese schneller eingebetteter Systeme. Universität Stuttgart.
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1997 | Misc | LibreCat-ID: 13090
Hertwig, A., Hellebrand, S., & Wunderlich, H.-J. (1997). Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. 3rd IEEE International On-Line Testing Workshop, Crete, Greece.
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1997 | Misc | LibreCat-ID: 13089
Tsai, K.-H., Hellebrand, S., Rajski, J., & Marek-Sadowska, M. (1997). STARBIST: Scan Autocorrelated Random Pattern Generation. 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA.
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1997 | Conference Paper | LibreCat-ID: 13009
Tsai, K.-H., Hellebrand, S., Marek-Sadowska, M., & Rajski, J. (1997). STARBIST: Scan Autocorrelated Random Pattern Generation. In {34th ACM/IEEE Design Automation Conference (DAC’97)}. Anaheim, CA, USA: {IEEE}. https://doi.org/10.1109/dac.1997.597194
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1996 | Misc | LibreCat-ID: 13087
Hellebrand, S., & Wunderlich, H.-J. (1996). Using Embedded Processors for BIST. 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA.
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1996 | Misc | LibreCat-ID: 13088
Hellebrand, S., Wunderlich, H.-J., & Hertwig, A. (1996). Mixed-Mode BIST Using Embedded Processors. 2nd IEEE International On-Line Testing Workshop. Biarritz, France.
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1996 | Conference Paper | LibreCat-ID: 13010
Hellebrand, S., Wunderlich, H.-J., & Hertwig, A. (1996). Mixed-Mode BIST Using Embedded Processors. In {IEEE International Test Conference (ITC’96)} (pp. 195–204). Washington, DC, USA: {IEEE}. https://doi.org/10.1109/test.1996.556962
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1995 | Report | LibreCat-ID: 13026
Hellebrand, S., & Wunderlich, H.-J. (1995). Synthesis Procedures for Self-Testable Controllers. University of Siegen, Germany.
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1995 | Report | LibreCat-ID: 13027
Hellebrand, S., Wunderlich, H.-J., Goncalves, F., & Paulo Teixeira, J. (1995). Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. University Siegen, Germany.
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1995 | Journal Article | LibreCat-ID: 13011
Hellebrand, S., Rajski, J., Tarnick, S., Venkataraman, S., & Courtois, B. (1995). Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. {IEEE Transactions on Computers}, 44(2), 223–233. https://doi.org/10.1109/12.364534
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