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167 Publications
1997 | Misc | LibreCat-ID: 13089
Tsai, Kun-Han, et al. STARBIST: Scan Autocorrelated Random Pattern Generation. 1997.
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1997 | Misc | LibreCat-ID: 13090
Hertwig, Andre, et al. Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. 1997.
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1997 | Conference Paper | LibreCat-ID: 13009
Tsai, Kun-Han, et al. “STARBIST: Scan Autocorrelated Random Pattern Generation.” 34th ACM/IEEE Design Automation Conference (DAC’97), IEEE, 1997, doi:10.1109/dac.1997.597194.
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1996 | Misc | LibreCat-ID: 13087
Hellebrand, Sybille, and Hans-Joachim Wunderlich. Using Embedded Processors for BIST. 1996.
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1996 | Misc | LibreCat-ID: 13088
Hellebrand, Sybille, et al. Mixed-Mode BIST Using Embedded Processors. 1996.
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1996 | Conference Paper | LibreCat-ID: 13010
Hellebrand, Sybille, et al. “Mixed-Mode BIST Using Embedded Processors.” IEEE International Test Conference (ITC’96), IEEE, 1996, pp. 195–204, doi:10.1109/test.1996.556962.
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1995 | Report | LibreCat-ID: 13026
Hellebrand, Sybille, and Hans-Joachim Wunderlich. Synthesis Procedures for Self-Testable Controllers. 1995.
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1995 | Report | LibreCat-ID: 13027
Hellebrand, Sybille, et al. Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. 1995.
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1995 | Report | LibreCat-ID: 13028
Hellebrand, Sybille, et al. Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. 1995.
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1995 | Misc | LibreCat-ID: 13086
Hellebrand, Sybille, et al. Pattern Generation for a Deterministic BIST Scheme. 1995.
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1995 | Journal Article | LibreCat-ID: 13011
Hellebrand, Sybille, et al. “Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers.” IEEE Transactions on Computers, vol. 44, no. 2, IEEE, 1995, pp. 223–33, doi:10.1109/12.364534.
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1995 | Conference Paper | LibreCat-ID: 13012
Hellebrand, Sybille, et al. “Pattern Generation for a Deterministic BIST Scheme.” ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), IEEE, 1995, pp. 88–94, doi:10.1109/iccad.1995.479997.
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1994 | Report | LibreCat-ID: 13024
Hellebrand, Sybille, et al. Synthesis for Off-Line Testability. 1994.
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1994 | Report | LibreCat-ID: 13025
Hellebrand, Sybille, et al. Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. 1994.
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1994 | Misc | LibreCat-ID: 13083
Venkataraman, Srikanth, et al. Effiziente Testsatzkodierung Für Prüfpfad-Basierte Selbsttestarchitekturen. 1994.
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1994 | Misc | LibreCat-ID: 13084
Hellebrand, Sybille, and Hans-Joachim Wunderlich. Ein Verfahren Zur Testfreundlichen Steuerwerkssynthese. 1994.
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1994 | Misc | LibreCat-ID: 13085
Hellebrand, Sybille, et al. Synthesis for Testability - the ARCHIMEDES Approach. 1994.
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1994 | Conference Paper | LibreCat-ID: 13014
Hellebrand, Sybille, and Hans-Joachim Wunderlich. “An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures.” ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), IEEE, 1994, pp. 110–16, doi:10.1109/iccad.1994.629752.
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1994 | Conference Paper | LibreCat-ID: 13059
Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Synthese Schneller Selbsttestbarer Steuerwerke.” Tagungsband Der GI/GME/ITG-Fachtagung \& Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme, 1994, pp. 3–11.
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1994 | Conference Paper | LibreCat-ID: 13013
Hellebrand, Sybille, and Hans-Joachim Wunderlich. “Synthesis of Self-Testable Controllers.” European Design and Test Conference (EDAC/ETC/EUROASIC), 1994, pp. 580–85, doi:10.1109/edtc.1994.326815.
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