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226 Publications
2023 | Conference Paper | LibreCat-ID: 44194 | 
Ahmed, Q. A., Awais, M., & Platzner, M. (2023). MAAS: Hiding Trojans in Approximate Circuits. The 24th International Symposium on Quality Electronic Design (ISQED’23), San Francisco, Califorina USA. The 24th International Symposium on Quality Electronic Design (ISQED’23), San Fransico CA 94023-0607, USA.
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2023 | Conference Paper | LibreCat-ID: 53794
Lienen, C., Brede, M., Karger, D., Koch, K., Logan, D., Mazur, J., Nowosad, A. P., Schnelle, A., Waizy, M., & Platzner, M. (2023). AutonomROS: A ReconROS-based Autonomous Driving Unit. 2023 Seventh IEEE International Conference on Robotic Computing (IRC). https://doi.org/10.1109/irc59093.2023.00056
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2023 | Conference Paper | LibreCat-ID: 45913
Clausing, L., Guetattfi, Z., Kaufmann, P., Lienen, C., & Platzner, M. (2023). On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64. Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC). https://doi.org/10.1007/978-3-031-42921-7_17
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2023 | Conference Paper | LibreCat-ID: 46229
Lienen, C., Nowosad, A. P., & Platzner, M. (n.d.). Mapping and Optimizing Communication in ROS 2-based Applications on Configurable System-on-Chip Platforms. Proceedings of the 2023 9th International Conference on Robotics and Artificial Intelligence (ICRAI). https://doi.org/10.1145/3637843.3637846
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2023 | Conference Paper | LibreCat-ID: 43048
Lienen, C., Middeke, S. H., & Platzner, M. (2023). fpgaDDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications. Proceedings of the 2023 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS). https://doi.org/10.1109/IROS55552.2023.10341921
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2022 | Conference Paper | LibreCat-ID: 29945
Witschen, L. M., Wiersema, T., Reuter, L. D., & Platzner, M. (n.d.). Search Space Characterization for Approximate Logic Synthesis . 2022 59th ACM/IEEE Design Automation Conference (DAC). 2022 59th ACM/IEEE Design Automation Conference (DAC), San Francisco, USA.
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2022 | Conference Paper | LibreCat-ID: 29865
Witschen, L. M., Wiersema, T., Artmann, M., & Platzner, M. (n.d.). MUSCAT: MUS-based Circuit Approximation Technique. Design, Automation and Test in Europe (DATE). Design, Automation and Test in Europe (DATE), Online.
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2022 | Conference Paper | LibreCat-ID: 30971
Hansmeier, T., & Platzner, M. (2022). Integrating Safety Guarantees into the Learning Classifier System XCS. Applications of Evolutionary Computation, EvoApplications 2022, Proceedings, 13224, 386–401. https://doi.org/10.1007/978-3-031-02462-7_25
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2022 | Conference Paper | LibreCat-ID: 32855
Clausing, L., & Platzner, M. (2022). ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support. 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 120–127. https://doi.org/10.1109/ipdpsw55747.2022.00029
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2022 | Conference Paper | LibreCat-ID: 33253
Hansmeier, T., Brede, M., & Platzner, M. (2022). XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion. GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion, 2071–2079. https://doi.org/10.1145/3520304.3533977
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2022 | Preprint | LibreCat-ID: 29541
Lienen, C., & Platzner, M. (2022). ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications.
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2022 | Conference Paper | LibreCat-ID: 34007
Lienen, C., & Platzner, M. (n.d.). Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS. 2022 Sixth IEEE International Conference on Robotic Computing (IRC) , Neaples, Italy.
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2022 | Conference Paper | LibreCat-ID: 34005
Lienen, C., & Platzner, M. (n.d.). Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications. 2022 25th Euromicro Conference on Digital System Design (DSD). 25th Euromicro Conference on Digital System Design (DSD), Maspalomas, Gran Canaria, Spain. https://doi.org/10.1109/DSD57027.2022.00088
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2022 | Conference Paper | LibreCat-ID: 32342
Ahmed, Q. A., & Platzner, M. (2022). On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs. IEEE Computer Society Annual Symposium on VLSI Aliathon Resort, Pafos, Cyprus.
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2021 | Conference Paper | LibreCat-ID: 21610
Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2021). LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis. In Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021 (pp. 27–32). Virtual: ACM. https://doi.org/10.1145/3453688.3461506
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2021 | Conference Paper | LibreCat-ID: 22309
Awais, M., & Platzner, M. (2021). MCTS-Based Synthesis Towards Efficient Approximate Accelerators. Proceedings of IEEE Computer Society Annual Symposium on VLSI, 384–389.
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2021 | Conference Paper | LibreCat-ID: 21953
Witschen, L. M., Wiersema, T., Raeisi Nafchi, M., Bockhorn, A., & Platzner, M. (n.d.). Timing Optimization for Virtual FPGA Configurations. In F. Hannig, S. Derrien, P. Diniz, & D. Chillet (Eds.), Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21). Springer Lecture Notes in Computer Science. https://doi.org/10.1007/978-3-030-79025-7_4
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2021 | Conference Paper | LibreCat-ID: 29137
Hansmeier, T. (2021). Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS. HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART ’21), Online. https://doi.org/10.1145/3468044.3468055
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2021 | Preprint | LibreCat-ID: 22764 |
Lienen, C., & Platzner, M. (2021). Design of Distributed Reconfigurable Robotics Systems with ReconROS. In arXiv:2107.07208.
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2021 | Conference Paper | LibreCat-ID: 21813
Hansmeier, T., & Platzner, M. (2021). An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS. GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion, 1639–1647. https://doi.org/10.1145/3449726.3463159
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2021 | Conference Paper | LibreCat-ID: 29138
Ahmed, Q. A. (2021). Hardware Trojans in Reconfigurable Computing. 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC). https://doi.org/10.1109/vlsi-soc53125.2021.9606974
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2021 | Conference Paper | LibreCat-ID: 20681 |
Ahmed, Q. A., Wiersema, T., & Platzner, M. (2021). Malicious Routing: Circumventing Bitstream-level Verification for FPGAs. 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). Design, Automation and Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France. https://doi.org/10.23919/DATE51398.2021.9474026
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2021 | Conference Paper | LibreCat-ID: 30909
Clausing, L. (2021). ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip. Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. https://doi.org/10.1145/3468044.3468056
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2021 | Conference Paper | LibreCat-ID: 30908
Ghasemzadeh Mohammadi, H., Jentzsch, F., Kuschel, M., Arshad, R., Rautmare, S., Manjunatha, S., Platzner, M., Boschmann, A., & Schollbach, D. (2021). FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics. Machine Learning and Principles and Practice of Knowledge Discovery in Databases. https://doi.org/10.1007/978-3-030-93736-2_27
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2020 | Conference Paper | LibreCat-ID: 3583
Guetttatfi, Z., Kaufmann, P., & Platzner, M. (2020). Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices. In Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC).
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2020 | Conference Paper | LibreCat-ID: 21584
Gatica, C. P., & Platzner, M. (2020). Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures. In Machine Learning for Cyber Physical Systems (ML4CPS 2017). Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-59084-3_9
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| DOI
2020 | Preprint | LibreCat-ID: 20748
Witschen, L. M., Wiersema, T., & Platzner, M. (n.d.). Search Space Characterization for AxC Synthesis. Fifth Workshop on Approximate Computing (AxC 2020).
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2020 | Conference Paper | LibreCat-ID: 20750
Lienen, C., Platzner, M., & Rinner, B. (2020). ReconROS: Flexible Hardware Acceleration for ROS2 Applications. In Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT).
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2020 | Conference Paper | LibreCat-ID: 17063
Hansmeier, T., Kaufmann, P., & Platzner, M. (2020). An Adaption Mechanism for the Error Threshold of XCSF. GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, 1756–1764. https://doi.org/10.1145/3377929.3398106
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2020 | Conference Paper | LibreCat-ID: 16213
Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2020). A Hybrid Synthesis Methodology for Approximate Circuits. In Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020 (pp. 421–426). Beijing, China: ACM. https://doi.org/10.1145/3386263.3406952
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2020 | Conference Paper | LibreCat-ID: 16363
Hansmeier, T., Kaufmann, P., & Platzner, M. (2020). Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold. In GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion (pp. 125–126). New York, NY, United States: Association for Computing Machinery (ACM). https://doi.org/10.1145/3377929.3389968
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2020 | Conference Paper | LibreCat-ID: 20838
Lösch, A., & Platzner, M. (2020). MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes. 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). https://doi.org/10.1109/ipdpsw50202.2020.00012
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2020 | Conference Paper | LibreCat-ID: 35152
Lösch, A., & Platzner, M. (2020). MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes. 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 6–16. https://doi.org/10.1109/IPDPSW50202.2020.00012
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| DOI
2019 | Preprint | LibreCat-ID: 16853
Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., & Platzner, M. (n.d.). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. Fourth Workshop on Approximate Computing (AxC 2019).
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2019 | Conference Paper | LibreCat-ID: 10577
Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., & Platzner, M. (2019). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits. In Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19. New York, NY, USA: ACM. https://doi.org/10.1145/3299874.3317998
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2019 | Conference Paper | LibreCat-ID: 15422
Ho, N., Kaufmann, P., & Platzner, M. (2019). Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor. In World Congress on Nature and Biologically Inspired Computing (NaBIC). Springer.
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2019 | Conference Paper | LibreCat-ID: 31067
Guettatfi, Z., Platzner, M., Kermia, O., & Khouas, A. (2019). An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware. 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). https://doi.org/10.1109/ipdpsw.2019.00027
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2019 | Conference Paper | LibreCat-ID: 9913 |
Ahmed, Q. A., Wiersema, T., & Platzner, M. (2019). Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan. In C. Hochberger, B. Nelson, A. Koch, R. Woods, & P. Diniz (Eds.), Applied Reconfigurable Computing (Vol. 11444, pp. 127–136). Springer International Publishing. https://doi.org/10.1007/978-3-030-17227-5_10
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2018 | Conference Paper | LibreCat-ID: 3362
Lösch, A., Wiens, A., & Platzner, M. (2018). Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes. In Proceedings of the International Conference on Architecture of Computing Systems (ARCS) (Vol. 10793, pp. 73–84). Cham: Springer International Publishing. https://doi.org/10.1007/978-3-319-77610-1_6
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2018 | Conference Paper | LibreCat-ID: 3373
Hansmeier, T., Platzner, M., & Andrews, D. (2018). An FPGA/HMC-Based Accelerator for Resolution Proof Checking. In ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications (Vol. 10824, pp. 153–165). Santorini, Greece: Springer International Publishing. https://doi.org/10.1007/978-3-319-78890-6_13
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2018 | Preprint | LibreCat-ID: 3586
Witschen, L. M., Wiersema, T., Ghasemzadeh Mohammadi, H., Awais, M., & Platzner, M. (n.d.). CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation. Third Workshop on Approximate Computing (AxC 2018).
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2018 | Preprint | LibreCat-ID: 1165
Witschen, L. M., Wiersema, T., & Platzner, M. (2018). Making the Case for Proof-carrying Approximate Circuits. 4th Workshop On Approximate Computing (WAPCO 2018).
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2018 | Conference Paper | LibreCat-ID: 5547
Lösch, A., & Platzner, M. (2018). A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes. In 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP). Milan, Italy: IEEE. https://doi.org/10.1109/asap.2018.8445098
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2018 | Conference Paper | LibreCat-ID: 10598
Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2018). An MCTS-based Framework for Synthesis of Approximate Circuits. In 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (pp. 219–224). https://doi.org/10.1109/VLSI-SoC.2018.8645026
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2017 | Conference Paper | LibreCat-ID: 65
Lösch, A., & Platzner, M. (2017). reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements. In Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP). https://doi.org/10.1109/ASAP.2017.7995272
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2017 | Conference Paper | LibreCat-ID: 10630
Boschmann, A., Thombansen, G., Witschen, L. M., Wiens, A., & Platzner, M. (2017). A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller. In Design, Automation and Test in Europe (DATE). https://doi.org/10.23919/DATE.2017.7927137
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2017 | Conference Paper | LibreCat-ID: 10672
Ho, N., Ashraf, I. I., Kaufmann, P., & Platzner, M. (2017). Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor. In Proc. Design, Automation and Test in Europe Conf. (DATE). https://doi.org/10.23919/DATE.2017.7927096
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2017 | Conference Paper | LibreCat-ID: 10676
Ho, N., Kaufmann, P., & Platzner, M. (2017). Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In 2017 International Conference on Field Programmable Technology (ICFPT) (pp. 215–218). https://doi.org/10.1109/FPT.2017.8280144
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2017 | Conference Paper | LibreCat-ID: 10760
Kaufmann, P., & Kalkreuth, R. (2017). Parametrizing Cartesian Genetic Programming: An Empirical Study. In KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI. Springer International Publishing. https://doi.org/10.1007/978-3-319-67190-1_26
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2017 | Conference Paper | LibreCat-ID: 10761
Kaufmann, P., Ho, N., & Platzner, M. (2017). Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches. In Adaptive Hardware and Systems (AHS). IEEE. https://doi.org/10.1109/AHS.2017.8046380
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2017 | Conference Paper | LibreCat-ID: 10762
Kaufmann, P., & Kalkreuth, R. (2017). An Empirical Study on the Parametrization of Cartesian Genetic Programming. In Genetic and Evolutionary Computation (GECCO), Compendium. ACM. https://doi.org/10.1145/3067695.3075980
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2017 | Conference Paper | LibreCat-ID: 10780
Guettatfi, Z., Hübner, P., Platzner, M., & Rinner, B. (2017). Computational self-awareness as design approach for visual sensor nodes. In 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) (pp. 1–8). https://doi.org/10.1109/ReCoSoC.2017.8016147
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2017 | Conference Paper | LibreCat-ID: 14893
Ghribi, I., Abdallah, R. B., Khalgui, M., & Platzner, M. (2017). I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems. In Communications in Computer and Information Science. Cham: Springer . https://doi.org/10.1007/978-3-319-62569-0_8
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2016 | Conference Paper | LibreCat-ID: 5812
Boschmann, A., Agne, A., Witschen, L., Thombansen, G., Kraus, F., & Platzner, M. (2016). FPGA-based acceleration of high density myoelectric signal processing. In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE. https://doi.org/10.1109/reconfig.2015.7393312
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2016 | Conference Paper | LibreCat-ID: 10622
Anwer, J., & Platzner, M. (2016). Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs. In Euromicro Conference on Digital System Design (DSD). https://doi.org/10.1109/DSD.2016.35
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2016 | Conference Paper | LibreCat-ID: 10631
Boschmann, A., Dosen, S., Werner, A., Raies, A., & Farina, D. (2016). A novel immersive augmented reality system for prosthesis training and assessment. In Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI).
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2016 | Conference Paper | LibreCat-ID: 10712
Meisner, S., & Platzner, M. (2016). Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level. In Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference on (pp. 1–8). https://doi.org/10.1109/ReConFig.2016.7857193
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2016 | Conference Paper | LibreCat-ID: 10766
Ghribi, I., Ben Abdallah, R., Khalgui, M., & Platzner, M. (2016). RCo-Design: New Visual Environment for Reconfigurable Embedded Systems. In Proceedings of the 30th European Simulation and Modelling Conference (ESM).
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2016 | Conference Paper | LibreCat-ID: 10768
Ghribi, I., Ben Abdallah, R., Khalgui, M., & Platzner, M. (2016). New Co-design Methodology for Real-time Embedded Systems. In Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA) (pp. 185–195).
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2016 | Conference Paper | LibreCat-ID: 15873
Boschmann, A., Agne, A., Witschen, L. M., Thombansen, G., Kraus, F., & Platzner, M. (2016). FPGA-based acceleration of high density myoelectric signal processing. In 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig). Mexiko City, Mexiko: IEEE. https://doi.org/10.1109/reconfig.2015.7393312
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2016 | Conference Paper | LibreCat-ID: 13151
Graf, T., & Platzner, M. (2016). Using Deep Convolutional Neural Networks in Monte Carlo Tree Search. In Computer and Games.
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2016 | Conference Paper | LibreCat-ID: 13152
Graf, T., & Platzner, M. (2016). Monte-Carlo Simulation Balancing Revisited. In IEEE Computational Intelligence and Games.
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2016 | Conference Paper | LibreCat-ID: 132
Wiersema, T., & Platzner, M. (2016). Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware. In Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016) (pp. 1--8). https://doi.org/10.1109/ReCoSoC.2016.7533910
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2016 | Conference Paper | LibreCat-ID: 168
Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–917.
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2015 | Conference Paper | LibreCat-ID: 269
Wiersema, T., Wu, S., & Platzner, M. (2015). On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach. In Proceedings of the International Symposium in Reconfigurable Computing (ARC) (pp. 365--372). https://doi.org/10.1007/978-3-319-16214-0_32
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2015 | Conference Paper | LibreCat-ID: 10673
Ho, N., Ahmed, A. F., Kaufmann, P., & Platzner, M. (2015). Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS) (pp. 1–7). https://doi.org/10.1109/AHS.2015.7231178
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2015 | Conference Paper | LibreCat-ID: 10693
Kaufmann, P., & Shen, C. (2015). Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing. In Genetic and Evolutionary Computation (GECCO) (pp. 409–416). ACM.
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2015 | Conference Paper | LibreCat-ID: 10711
Meisner, S., & Platzner, M. (2015). Comparison of thread signatures for error detection in hybrid multi-cores. In Field Programmable Technology (FPT), 2015 International Conference on (pp. 212–215). https://doi.org/10.1109/FPT.2015.7393153
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2015 | Conference Paper | LibreCat-ID: 10765
H.W. Leong, P., Amano, H., Anderson, J., Bertels, K., M.P. Cardoso, J., Diessel, O., … Wang, Y. (2015). Significant papers from the first 25 years of the FPL conference. In Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL) (pp. 1–3). Imperial College. https://doi.org/10.1109/FPL.2015.7293747
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2015 | Conference Paper | LibreCat-ID: 10767
Ghribi, I., Ben Abdallah, R., Khalgui, M., & Platzner, M. (2015). New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software. In Proceedings of the 29th European Simulation and Modelling Conference (ESM).
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2015 | Conference Paper | LibreCat-ID: 10771
Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Zhang, J., De Micheli, G., Sanchez, E., & Reorda, M. S. (2015). On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors. In 2015 IEEE Computer Society Annual Symposium on VLSI (pp. 491–496). IEEE. https://doi.org/10.1109/ISVLSI.2015.13
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2015 | Conference Paper | LibreCat-ID: 10772
Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., & De Micheli, G. (2015). Fault modeling in controllable polarity silicon nanowire circuits. In Proceedings of the 2015 Design, Automation & Test in Europe Conference \& Exhibition (pp. 453–458). EDA Consortium. https://doi.org/10.7873/DATE.2015.0428
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2015 | Conference Paper | LibreCat-ID: 10779
Guettatfi, Z., Kermia, O., & Khouas, A. (2015). Over effective hard real-time hardware tasks scheduling and allocation. In 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College. https://doi.org/10.1109/FPL.2015.7293994
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2015 | Conference Paper | LibreCat-ID: 13153
Graf, T., & Platzner, M. (2015). Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning. In Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers (pp. 1–11). Springer International Publishing. https://doi.org/10.1007/978-3-319-27992-3_1
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2015 | Conference Paper | LibreCat-ID: 303 |
Damschen, M., & Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT).
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| arXiv
2015 | Conference Paper | LibreCat-ID: 1773
Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). https://doi.org/10.1145/2675743.2771824
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2015 | Conference Paper | LibreCat-ID: 238
Damschen, M., Riebler, H., Vaz, G. F., & Plessl, C. (2015). Transparent offloading of computational hotspots from binary code to Xeon Phi. Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083. https://doi.org/10.7873/DATE.2015.1124
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2014 | Conference Paper | LibreCat-ID: 347
Meisner, S., & Platzner, M. (2014). Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection. In D. Goehringer, M. Santambrogio, J. P. Cardoso, & K. Bertels (Eds.), Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC) (pp. 283–290). Springer. https://doi.org/10.1007/978-3-319-05960-0_30
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2014 | Conference Paper | LibreCat-ID: 1782
Graf, T., Schaefers, L., & Platzner, M. (2014). On Semeai Detection in Monte-Carlo Go. In Proc. Conf. on Computers and Games (CG) (pp. 14–25). Switzerland: Springer. https://doi.org/10.1007/978-3-319-09165-5_2
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2014 | Conference Paper | LibreCat-ID: 399
Wiersema, T., Drzevitzky, S., & Platzner, M. (2014). Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring. In Proceedings of the International Conference on Field-Programmable Technology (FPT) (pp. 167–174). https://doi.org/10.1109/FPT.2014.7082771
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2014 | Conference Paper | LibreCat-ID: 408
Jakobs, M.-C., Platzner, M., Wiersema, T., & Wehrheim, H. (2014). Integrating Software and Hardware Verification. In E. Albert & E. Sekerinski (Eds.), Proceedings of the 11th International Conference on Integrated Formal Methods (iFM) (pp. 307–322). https://doi.org/10.1007/978-3-319-10181-1_19
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2014 | Conference Paper | LibreCat-ID: 433
Wiersema, T., Bockhorn, A., & Platzner, M. (2014). Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA. In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) (pp. 1–6). https://doi.org/10.1109/ReConFig.2014.7032514
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2014 | Conference Paper | LibreCat-ID: 10621
Anwer, J., Platzner, M., & Meisner, S. (2014). FPGA Redundancy Configurations: An Automated Design Space Exploration. In Reconfigurable Architectures Workshop (RAW). https://doi.org/10.1109/IPDPSW.2014.37
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2014 | Conference Paper | LibreCat-ID: 10632
Boschmann, A., & Platzner, M. (2014). A computer vision-based approach to high density EMG pattern recognition using structural similarity. In Proc. MyoElectric Controls Symposium (MEC).
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2014 | Conference Paper | LibreCat-ID: 10633
Boschmann, A., & Platzner, M. (2014). Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity. In Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC).
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2014 | Conference Paper | LibreCat-ID: 10654
Glette, K., & Kaufmann, P. (2014). Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System. In IEEE Congress on Evolutionary Computation (CEC).
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2014 | Conference Paper | LibreCat-ID: 10674
Ho, N., Kaufmann, P., & Platzner, M. (2014). A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In 24th Intl. Conf. on Field Programmable Logic and Applications (FPL) (pp. 1–4). https://doi.org/10.1109/FPL.2014.6927437
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2014 | Conference Paper | LibreCat-ID: 10677
Ho, N., Kaufmann, P., & Platzner, M. (2014). Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES) (pp. 31–37). https://doi.org/10.1109/ICES.2014.7008719
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2014 | Conference Paper | LibreCat-ID: 10738
Shen, C., Kaufmann, P., & Braun, M. (2014). Optimizing the Generator Start-up Sequence After a Power System Blackout. In IEEE Power and Energy Society General Meeting (IEEE GM).
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2014 | Conference Paper | LibreCat-ID: 10739
Shen, C., Kaufmann, P., & Braun, M. (2014). A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm. In Power Systems Computation Conference (PSCC). IEEE.
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2014 | Conference Paper | LibreCat-ID: 10764
Anwer, J., & Platzner, M. (2014). Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs. In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (pp. 177–184). IEEE. https://doi.org/10.1109/DFT.2014.6962108
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2014 | Conference Paper | LibreCat-ID: 10773
Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Yazdani, M., & De Micheli, G. (2014). Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection. In 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) (pp. 163–168). IEEE. https://doi.org/10.1109/NANOARCH.2014.6880479
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2014 | Conference Paper | LibreCat-ID: 13154
Graf, T., & Platzner, M. (2014). Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go. In 2014 IEEE Conference on Computational Intelligence and Games (pp. 1–8). https://doi.org/10.1109/CIG.2014.6932863
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2014 | Conference Paper | LibreCat-ID: 388
Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13
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| DOI
2014 | Conference Paper | LibreCat-ID: 377
Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67
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| DOI
2014 | Conference Paper | LibreCat-ID: 1778
C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–149. https://doi.org/10.1109/ISPA.2014.27
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2014 | Conference Paper | LibreCat-ID: 439
Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509
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| DOI
2014 | Conference Paper | LibreCat-ID: 406
Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535
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| DOI
2014 | Conference Paper | LibreCat-ID: 1780
C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino, M., Pell, O., Plessl, C., D. Santambrogio, M., & Bolchini, C. (2014). SAVE: Towards efficient resource management in heterogeneous system architectures. Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). https://doi.org/10.1007/978-3-319-05960-0_38
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2013 | Conference Paper | LibreCat-ID: 1786
Kasap, S., & Redif, S. (2013). FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE. https://doi.org/10.1109/SIU.2013.6531530
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