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165 Publications


2023 | Conference Paper | LibreCat-ID: 45830
Jafarzadeh H, Klemme F, Reimer JD, et al. Robust Pattern Generation for Small Delay Faults under Process Variations. In: IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023. IEEE; 2023.
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2022 | Journal Article | LibreCat-ID: 29351
Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Stress-Aware Periodic Test of Interconnects. Journal of Electronic Testing. Published online 2022. doi:10.1007/s10836-021-05979-5
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2022 | Misc | LibreCat-ID: 29890
Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. EM-Aware Interconnect BIST. European Workshop on Silicon Lifecycle Management, March 18, 2022; 2022.
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2020 | Conference Paper | LibreCat-ID: 19422
Sprenger A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020. ; 2020.
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2020 | Misc | LibreCat-ID: 15419
Sadeghi-Kohan S, Hellebrand S. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020; 2020.
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2020 | Conference Paper | LibreCat-ID: 29200
Sadeghi-Kohan S, Hellebrand S. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. In: 38th IEEE VLSI Test Symposium (VTS). IEEE; 2020. doi:10.1109/vts48691.2020.9107591
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2020 | Conference Paper | LibreCat-ID: 19421
Holst S, Kampmann M, Sprenger A, et al. Logic Fault Diagnosis of Hidden Delay Defects. In: IEEE International Test Conference (ITC’20), November 2020. ; 2020.
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2019 | Misc | LibreCat-ID: 8112
Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19); 2019.
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2019 | Journal Article | LibreCat-ID: 8667
Sprenger A, Hellebrand S. Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. Journal of Circuits, Systems and Computers. 2019;28(1):1-23. doi:10.1142/s0218126619400012
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2019 | Journal Article | LibreCat-ID: 13048
Kampmann M, A. Kochte M, Liu C, Schneider E, Hellebrand S, Wunderlich H-J. Built-in Test for Hidden Delay Faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). 2019;38(10):1956-1968.
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2019 | Conference Paper | LibreCat-ID: 12918
Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Adaptive X-Handling. In: 50th IEEE International Test Conference (ITC). IEEE; 2019:1-8.
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2018 | Misc | LibreCat-ID: 4576
Sprenger A, Hellebrand S. Stochastische Kompaktierung für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18); 2018.
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2018 | Journal Article | LibreCat-ID: 12974
Hellebrand S, Henkel J, Raghunathan A, Wunderlich H-J. Guest Editors’ Introduction - Special Issue on Approximate Computing. IEEE Embedded Systems Letters. 2018;10(1):1-1. doi:10.1109/les.2018.2789942
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2018 | Journal Article | LibreCat-ID: 13057
Kampmann M, Hellebrand S. Design For Small Delay Test - A Simulation Study. Microelectronics Reliability. 2018;80:124-133.
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2018 | Misc | LibreCat-ID: 13072
Kampmann M, Hellebrand S. Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test. 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China; 2018.
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2018 | Conference Paper | LibreCat-ID: 29460
Rezaeizadeh Rookerd R, Sadeghi-Kohan S, Navabi Z. Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture. In: Proceedings of the 2018 on Great Lakes Symposium on VLSI. ACM; 2018. doi:10.1145/3194554.3194599
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2018 | Conference Paper | LibreCat-ID: 4575
Sprenger A, Hellebrand S. Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. In: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE; 2018. doi:10.1109/ddecs.2018.00020
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2018 | Conference Paper | LibreCat-ID: 10575
Liu C, Schneider E, Kampmann M, Hellebrand S, Wunderlich H-J. Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. In: 27th IEEE Asian Test Symposium (ATS’18). ; 2018. doi:10.1109/ats.2018.00028
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2018 | Conference Paper | LibreCat-ID: 29459
Sadeghi-Kohan S, Vafaei A, Navabi Z. Near-Optimal Node Selection Procedure for Aging Monitor Placement. In: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS). IEEE; 2018. doi:10.1109/iolts.2018.8474120
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2017 | Conference Paper | LibreCat-ID: 12973
Deshmukh J, Kunz W, Wunderlich H-J, Hellebrand S. Special Session on Early Life Failures. In: 35th IEEE VLSI Test Symposium (VTS’17). Caesars Palace, Las Vegas, Nevada, USA: IEEE; 2017. doi:10.1109/vts.2017.7928933
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