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165 Publications
2023 | Conference Paper | LibreCat-ID: 45830
Robust Pattern Generation for Small Delay Faults under Process Variations
H. Jafarzadeh, F. Klemme, J.D. Reimer, Z.P. Najafi Haghi, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023, IEEE, Anaheim, CA, USA, 2023.
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H. Jafarzadeh, F. Klemme, J.D. Reimer, Z.P. Najafi Haghi, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023, IEEE, Anaheim, CA, USA, 2023.
2022 | Journal Article | LibreCat-ID: 29351
Stress-Aware Periodic Test of Interconnects
S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing (2022).
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| DOI
S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing (2022).
2022 | Misc | LibreCat-ID: 29890
EM-Aware Interconnect BIST
S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, EM-Aware Interconnect BIST, European Workshop on Silicon Lifecycle Management, March 18, 2022, Online, 2022.
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S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, EM-Aware Interconnect BIST, European Workshop on Silicon Lifecycle Management, March 18, 2022, Online, 2022.
2020 | Conference Paper | LibreCat-ID: 19422
Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study
A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, Virtual Conference - Originally Frascati (Rome), Italy, 2020.
LibreCat
A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, Virtual Conference - Originally Frascati (Rome), Italy, 2020.
2020 | Misc | LibreCat-ID: 15419
Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects
S. Sadeghi-Kohan, S. Hellebrand, Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects, 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, Ludwigsburg, 2020.
LibreCat
S. Sadeghi-Kohan, S. Hellebrand, Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects, 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, Ludwigsburg, 2020.
2020 | Conference Paper | LibreCat-ID: 29200
Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects
S. Sadeghi-Kohan, S. Hellebrand, in: 38th IEEE VLSI Test Symposium (VTS), IEEE, Virtual Conference - Originally San Diego, CA, USA, 2020.
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S. Sadeghi-Kohan, S. Hellebrand, in: 38th IEEE VLSI Test Symposium (VTS), IEEE, Virtual Conference - Originally San Diego, CA, USA, 2020.
2020 | Conference Paper | LibreCat-ID: 19421
Logic Fault Diagnosis of Hidden Delay Defects
S. Holst, M. Kampmann, A. Sprenger, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, X. Weng, in: IEEE International Test Conference (ITC’20), November 2020, Virtual Conference - Originally Washington, DC, USA, 2020.
LibreCat
S. Holst, M. Kampmann, A. Sprenger, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, X. Weng, in: IEEE International Test Conference (ITC’20), November 2020, Virtual Conference - Originally Washington, DC, USA, 2020.
2019 | Misc | LibreCat-ID: 8112
A Hybrid Space Compactor for Varying X-Rates
M.U. Maaz, A. Sprenger, S. Hellebrand, A Hybrid Space Compactor for Varying X-Rates, 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), Prien am Chiemsee, 2019.
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M.U. Maaz, A. Sprenger, S. Hellebrand, A Hybrid Space Compactor for Varying X-Rates, 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), Prien am Chiemsee, 2019.
2019 | Journal Article | LibreCat-ID: 8667
Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test
A. Sprenger, S. Hellebrand, Journal of Circuits, Systems and Computers 28 (2019) 1–23.
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| DOI
A. Sprenger, S. Hellebrand, Journal of Circuits, Systems and Computers 28 (2019) 1–23.
2019 | Journal Article | LibreCat-ID: 13048
Built-in Test for Hidden Delay Faults
M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, H.-J. Wunderlich, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38 (2019) 1956–1968.
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M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, H.-J. Wunderlich, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38 (2019) 1956–1968.
2019 | Conference Paper | LibreCat-ID: 12918
A Hybrid Space Compactor for Adaptive X-Handling
M.U. Maaz, A. Sprenger, S. Hellebrand, in: 50th IEEE International Test Conference (ITC), IEEE, Washington, DC, USA, 2019, pp. 1–8.
LibreCat
M.U. Maaz, A. Sprenger, S. Hellebrand, in: 50th IEEE International Test Conference (ITC), IEEE, Washington, DC, USA, 2019, pp. 1–8.
2018 | Misc | LibreCat-ID: 4576
Stochastische Kompaktierung für den Hochgeschwindigkeitstest
A. Sprenger, S. Hellebrand, Stochastische Kompaktierung für den Hochgeschwindigkeitstest, 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), Freiburg, Germany, 2018.
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A. Sprenger, S. Hellebrand, Stochastische Kompaktierung für den Hochgeschwindigkeitstest, 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), Freiburg, Germany, 2018.
2018 | Journal Article | LibreCat-ID: 12974
Guest Editors' Introduction - Special Issue on Approximate Computing
S. Hellebrand, J. Henkel, A. Raghunathan, H.-J. Wunderlich, IEEE Embedded Systems Letters 10 (2018) 1–1.
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| DOI
S. Hellebrand, J. Henkel, A. Raghunathan, H.-J. Wunderlich, IEEE Embedded Systems Letters 10 (2018) 1–1.
2018 | Journal Article | LibreCat-ID: 13057
Design For Small Delay Test - A Simulation Study
M. Kampmann, S. Hellebrand, Microelectronics Reliability 80 (2018) 124–133.
LibreCat
M. Kampmann, S. Hellebrand, Microelectronics Reliability 80 (2018) 124–133.
2018 | Misc | LibreCat-ID: 13072
Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test
M. Kampmann, S. Hellebrand, Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test, 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China, 2018.
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M. Kampmann, S. Hellebrand, Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test, 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China, 2018.
2018 | Conference Paper | LibreCat-ID: 29460
Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture
R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, Z. Navabi, in: Proceedings of the 2018 on Great Lakes Symposium on VLSI, ACM, 2018.
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R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, Z. Navabi, in: Proceedings of the 2018 on Great Lakes Symposium on VLSI, ACM, 2018.
2018 | Conference Paper | LibreCat-ID: 4575
Tuning Stochastic Space Compaction to Faster-than-at-Speed Test
A. Sprenger, S. Hellebrand, in: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, Budapest, Hungary, 2018.
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A. Sprenger, S. Hellebrand, in: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, Budapest, Hungary, 2018.
2018 | Conference Paper | LibreCat-ID: 10575
Extending Aging Monitors for Early Life and Wear-Out Failure Prevention
C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, H.-J. Wunderlich, in: 27th IEEE Asian Test Symposium (ATS’18), 2018.
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C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, H.-J. Wunderlich, in: 27th IEEE Asian Test Symposium (ATS’18), 2018.
2018 | Conference Paper | LibreCat-ID: 29459
Near-Optimal Node Selection Procedure for Aging Monitor Placement
S. Sadeghi-Kohan, A. Vafaei, Z. Navabi, in: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), IEEE, 2018.
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S. Sadeghi-Kohan, A. Vafaei, Z. Navabi, in: 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), IEEE, 2018.
2017 | Conference Paper | LibreCat-ID: 12973
Special Session on Early Life Failures
J. Deshmukh, W. Kunz, H.-J. Wunderlich, S. Hellebrand, in: 35th IEEE VLSI Test Symposium (VTS’17), IEEE, Caesars Palace, Las Vegas, Nevada, USA, 2017.
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J. Deshmukh, W. Kunz, H.-J. Wunderlich, S. Hellebrand, in: 35th IEEE VLSI Test Symposium (VTS’17), IEEE, Caesars Palace, Las Vegas, Nevada, USA, 2017.