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165 Publications


2007 | Misc | LibreCat-ID: 13042
Oehler, P., Hellebrand, S., & Wunderlich, H.-J. (2007). An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany.
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2007 | Misc | LibreCat-ID: 13043
Hellebrand, S. (2007). Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden. ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany.
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2007 | Conference Paper | LibreCat-ID: 12995
Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., & Straube, B. (2007). A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), 50–58. https://doi.org/10.1109/dft.2007.43
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2007 | Conference Paper | LibreCat-ID: 12996
Oehler, P., Hellebrand, S., & Wunderlich, H.-J. (2007). Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), 185–190. https://doi.org/10.1109/ddecs.2007.4295278
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2007 | Conference Paper | LibreCat-ID: 12997
Oehler, P., Hellebrand, S., & Wunderlich, H.-J. (2007). An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. 12th IEEE European Test Symposium (ETS’07), 91–96. https://doi.org/10.1109/ets.2007.10
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2007 | Conference Paper | LibreCat-ID: 13037
Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., & Straube, B. (2007). Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper).
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2007 | Journal Article | LibreCat-ID: 13036
Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., & Straube, B. (2007). Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. Informacije MIDEM, Ljubljana (Invited Paper), 37(4 (124)), 212–219.
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2007 | Journal Article | LibreCat-ID: 13044
Ali, M., Hessler, S., Welzl, M., & Hellebrand, S. (2007). An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip. International Journal on High Performance Systems Architecture, 1(2), 113–123.
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2007 | Conference Paper | LibreCat-ID: 13040
Ali, M., Welzl, M., Hessler, S., & Hellebrand, S. (2007). A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip. 4th International Conference on Information Technology: New Generations (ITNG’07), 1027–1032.
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2007 | Conference Paper | LibreCat-ID: 13041
Becker, B., Polian, I., Hellebrand, S., Straube, B., & Wunderlich, H.-J. (2007). Test und Zuverlässigkeit nanoelektronischer Systeme. 1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”
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2006 | Journal Article | LibreCat-ID: 13045
Becker, B., Polian, I., Hellebrand, S., Straube, B., & Wunderlich, H.-J. (2006). DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme. It - Information Technology, 48(5), 305–311.
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2005 | Misc | LibreCat-ID: 13046
Oehler, P., & Hellebrand, S. (2005). A Low Power Design for Embedded DRAMs with Online Consistency Checking. Kleinheubachertagung 2005, Miltenberg, Germany.
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2005 | Misc | LibreCat-ID: 13101
Ali, M., Welzl, M., & Hellebrand, S. (2005). Dynamic Routing: A Prerequisite for Reliable NoCs. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria.
LibreCat
 

2005 | Misc | LibreCat-ID: 13102
Oehler, P., & Hellebrand, S. (2005). Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study. 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria.
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2005 | Conference Paper | LibreCat-ID: 12999
Ali, M., Welzl, M., Zwicknagl, M., & Hellebrand, S. (2005). Considerations for Fault-Tolerant Networks on Chips. IEEE International Conference on Microelectronics (ICM’05). https://doi.org/10.1109/icm.2005.1590063
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2005 | Conference Paper | LibreCat-ID: 13000
Oehler, P., & Hellebrand, S. (2005). Low Power Embedded DRAMs with High Quality Error Correcting Capabilities. 10th IEEE European Test Symposium (ETS’05), 148–153. https://doi.org/10.1109/ets.2005.28
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2005 | Conference Paper | LibreCat-ID: 12998
Ali, M., Welzl, M., & Hellebrand, S. (2005). A Dynamic Routing Mechanism for Network on Chip. 23rd IEEE NORCHIP Conference, 70–73. https://doi.org/10.1109/norchp.2005.1596991
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2004 | Conference Paper | LibreCat-ID: 13071
Liu Jing, M., Ruehrup, S., Schindelhauer, C., Volbert, K., Dierkes, M., Bellgardt, A., … Hilleringmann, U. (2004). Sensor Networks with More Features Using Less Hardware. In {GOR/NGB Conference Tilburg 2004}. Tilburg, Netherlands.
LibreCat
 

2004 | Misc | LibreCat-ID: 13099
Breu, R., Fahringer, T., Fensel, D., Hellebrand, S., Middeldorp, A., & Scherzer, O. (2004). Im Westen viel Neues - Informatik an der Universität Innsbruck. OCG Journal, pp. 28-29.
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2004 | Misc | LibreCat-ID: 13100
Hellebrand, S., Wuertenberger, A., & S. Tautermann, C. (2004). Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. 9th IEEE European Test Symposium, Ajaccio, Corsica, France.
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