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84 Publications
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2010 | Conference Paper | LibreCat-ID: 13049
Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., & Wunderlich, H.-J. (2010). Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper).
LibreCat
2010 | Conference Paper | LibreCat-ID: 13050
Indlekofer, T., Schnittger, M., & Hellebrand, S. (2010). Robuster Selbsttest mit extremer Kompaktierung. 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” 17–24.
LibreCat
2009 | Conference Paper | LibreCat-ID: 12991
Hunger, M., Hellebrand, S., Czutro, A., Polian, I., & Becker, B. (2009). ATPG-Based Grading of Strong Fault-Secureness. 15th IEEE International On-Line Testing Symposium (IOLTS’09. https://doi.org/10.1109/iolts.2009.5196027
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2009 | Conference Paper | LibreCat-ID: 12990
Hellebrand, S., & Hunger, M. (2009). Are Robust Circuits Really Robust? 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), 77. https://doi.org/10.1109/dft.2009.28
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2009 | Conference Paper | LibreCat-ID: 13030
Hunger, M., Hellebrand, S., Czutro, A., Polian, I., & Becker, B. (2009). Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung. 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”
LibreCat
2008 | Conference Paper | LibreCat-ID: 12992
Oehler, P., Bosio, A., di Natale, G., & Hellebrand, S. (2008). A Modular Memory BIST for Optimized Memory Repair. 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster). https://doi.org/10.1109/iolts.2008.30
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2008 | Conference Paper | LibreCat-ID: 12994
Amgalan, U., Hachmann, C., Hellebrand, S., & Wunderlich, H.-J. (2008). Signature Rollback - A Technique for Testing Robust Circuits. 26th IEEE VLSI Test Symposium (VTS’08), 125–130. https://doi.org/10.1109/vts.2008.34
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2008 | Conference Paper | LibreCat-ID: 12993
Hunger, M., & Hellebrand, S. (2008). Verification and Analysis of Self-Checking Properties through ATPG. 14th IEEE International On-Line Testing Symposium (IOLTS’08). https://doi.org/10.1109/iolts.2008.32
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2008 | Conference Paper | LibreCat-ID: 13031
Hunger, M., & Hellebrand, S. (2008). Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG. 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”
LibreCat
2008 | Conference Paper | LibreCat-ID: 13032
Oehler, P., Bosio, A., Di Natale, G., & Hellebrand, S. (2008). Modularer Selbsttest und optimierte Reparaturanalyse. 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”
LibreCat
2007 | Conference Paper | LibreCat-ID: 12995
Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., & Straube, B. (2007). A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), 50–58. https://doi.org/10.1109/dft.2007.43
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2007 | Conference Paper | LibreCat-ID: 12996
Oehler, P., Hellebrand, S., & Wunderlich, H.-J. (2007). Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), 185–190. https://doi.org/10.1109/ddecs.2007.4295278
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2007 | Conference Paper | LibreCat-ID: 12997
Oehler, P., Hellebrand, S., & Wunderlich, H.-J. (2007). An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. 12th IEEE European Test Symposium (ETS’07), 91–96. https://doi.org/10.1109/ets.2007.10
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2007 | Conference Paper | LibreCat-ID: 13037
Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., & Straube, B. (2007). Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper).
LibreCat
2007 | Conference Paper | LibreCat-ID: 13040
Ali, M., Welzl, M., Hessler, S., & Hellebrand, S. (2007). A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip. 4th International Conference on Information Technology: New Generations (ITNG’07), 1027–1032.
LibreCat
2007 | Conference Paper | LibreCat-ID: 13041
Becker, B., Polian, I., Hellebrand, S., Straube, B., & Wunderlich, H.-J. (2007). Test und Zuverlässigkeit nanoelektronischer Systeme. 1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.”
LibreCat
2005 | Conference Paper | LibreCat-ID: 12999
Ali, M., Welzl, M., Zwicknagl, M., & Hellebrand, S. (2005). Considerations for Fault-Tolerant Networks on Chips. IEEE International Conference on Microelectronics (ICM’05). https://doi.org/10.1109/icm.2005.1590063
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2005 | Conference Paper | LibreCat-ID: 13000
Oehler, P., & Hellebrand, S. (2005). Low Power Embedded DRAMs with High Quality Error Correcting Capabilities. 10th IEEE European Test Symposium (ETS’05), 148–153. https://doi.org/10.1109/ets.2005.28
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2005 | Conference Paper | LibreCat-ID: 12998
Ali, M., Welzl, M., & Hellebrand, S. (2005). A Dynamic Routing Mechanism for Network on Chip. 23rd IEEE NORCHIP Conference, 70–73. https://doi.org/10.1109/norchp.2005.1596991
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2004 | Conference Paper | LibreCat-ID: 13071
Liu Jing, M., Ruehrup, S., Schindelhauer, C., Volbert, K., Dierkes, M., Bellgardt, A., … Hilleringmann, U. (2004). Sensor Networks with More Features Using Less Hardware. In {GOR/NGB Conference Tilburg 2004}. Tilburg, Netherlands.
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