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84 Publications


2010 | Conference Paper | LibreCat-ID: 13049
Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper), Chicago, IL, USA, 2010.
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2010 | Conference Paper | LibreCat-ID: 13050
Robuster Selbsttest mit extremer Kompaktierung
T. Indlekofer, M. Schnittger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Wildbad Kreuth, Germany, 2010, pp. 17–24.
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2009 | Conference Paper | LibreCat-ID: 12991
ATPG-Based Grading of Strong Fault-Secureness
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: 15th IEEE International On-Line Testing Symposium (IOLTS’09, IEEE, Sesimbra-Lisbon, Portugal, 2009.
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2009 | Conference Paper | LibreCat-ID: 12990
Are Robust Circuits Really Robust?
S. Hellebrand, M. Hunger, in: 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk), IEEE, Chicago, IL, USA, 2009, p. 77.
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2009 | Conference Paper | LibreCat-ID: 13030
Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung
M. Hunger, S. Hellebrand, A. Czutro, I. Polian, B. Becker, in: 3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Stuttgart, Germany, 2009.
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2008 | Conference Paper | LibreCat-ID: 12992
A Modular Memory BIST for Optimized Memory Repair
P. Oehler, A. Bosio, G. di Natale, S. Hellebrand, in: 14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster), IEEE, Rhodos, Greece, 2008.
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2008 | Conference Paper | LibreCat-ID: 12994
Signature Rollback - A Technique for Testing Robust Circuits
U. Amgalan, C. Hachmann, S. Hellebrand, H.-J. Wunderlich, in: 26th IEEE VLSI Test Symposium (VTS’08), IEEE, San Diego, CA, USA, 2008, pp. 125–130.
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2008 | Conference Paper | LibreCat-ID: 12993
Verification and Analysis of Self-Checking Properties through ATPG
M. Hunger, S. Hellebrand, in: 14th IEEE International On-Line Testing Symposium (IOLTS’08), IEEE, Rhodos, Greece, 2008.
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2008 | Conference Paper | LibreCat-ID: 13031
Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG
M. Hunger, S. Hellebrand, in: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Ingolstadt, Germany, 2008.
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2008 | Conference Paper | LibreCat-ID: 13032
Modularer Selbsttest und optimierte Reparaturanalyse
P. Oehler, A. Bosio, G. Di Natale, S. Hellebrand, in: 2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Ingolstadt, Germany, 2008.
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2007 | Conference Paper | LibreCat-ID: 12995
A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07), IEEE, Rome, Italy, 2007, pp. 50–58.
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2007 | Conference Paper | LibreCat-ID: 12996
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), IEEE, Krakow, Poland, 2007, pp. 185–190.
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2007 | Conference Paper | LibreCat-ID: 12997
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy
P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: 12th IEEE European Test Symposium (ETS’07), IEEE, Freiburg, Germany, 2007, pp. 91–96.
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2007 | Conference Paper | LibreCat-ID: 13037
Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper), Bled, Slovenia, 2007.
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2007 | Conference Paper | LibreCat-ID: 13040
A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip
M. Ali, M. Welzl, S. Hessler, S. Hellebrand, in: 4th International Conference on Information Technology: New Generations (ITNG’07), Las Vegas, Nevada, USA, 2007, pp. 1027–1032.
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2007 | Conference Paper | LibreCat-ID: 13041
Test und Zuverlässigkeit nanoelektronischer Systeme
B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich, in: 1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Munich, Germany, 2007.
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2005 | Conference Paper | LibreCat-ID: 12999
Considerations for Fault-Tolerant Networks on Chips
M. Ali, M. Welzl, M. Zwicknagl, S. Hellebrand, in: IEEE International Conference on Microelectronics (ICM’05), IEEE, Islamabad, Pakistan, 2005.
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2005 | Conference Paper | LibreCat-ID: 13000
Low Power Embedded DRAMs with High Quality Error Correcting Capabilities
P. Oehler, S. Hellebrand, in: 10th IEEE European Test Symposium (ETS’05), IEEE, Tallinn, Estonia, 2005, pp. 148–153.
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2005 | Conference Paper | LibreCat-ID: 12998
A Dynamic Routing Mechanism for Network on Chip
M. Ali, M. Welzl, S. Hellebrand, in: 23rd IEEE NORCHIP Conference, IEEE, Oulu, Finland, 2005, pp. 70–73.
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2004 | Conference Paper | LibreCat-ID: 13071
Sensor Networks with More Features Using Less Hardware
M. Liu Jing, S. Ruehrup, C. Schindelhauer, K. Volbert, M. Dierkes, A. Bellgardt, R. Ibers, U. Hilleringmann, in: {GOR/NGB Conference Tilburg 2004}, Tilburg, Netherlands, 2004.
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