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24 Publications
2023 | Journal Article | LibreCat-ID: 46264
Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Workload-Aware Periodic Interconnect BIST. IEEE Design &Test. Published online 2023:1-1. doi:10.1109/mdat.2023.3298849
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2022 | Journal Article | LibreCat-ID: 29351
Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Stress-Aware Periodic Test of Interconnects. Journal of Electronic Testing. Published online 2022. doi:10.1007/s10836-021-05979-5
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2019 | Journal Article | LibreCat-ID: 8667
Sprenger A, Hellebrand S. Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. Journal of Circuits, Systems and Computers. 2019;28(1):1-23. doi:10.1142/s0218126619400012
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2019 | Journal Article | LibreCat-ID: 13048
Kampmann M, A. Kochte M, Liu C, Schneider E, Hellebrand S, Wunderlich H-J. Built-in Test for Hidden Delay Faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). 2019;38(10):1956-1968.
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2018 | Journal Article | LibreCat-ID: 12974
Hellebrand S, Henkel J, Raghunathan A, Wunderlich H-J. Guest Editors’ Introduction - Special Issue on Approximate Computing. IEEE Embedded Systems Letters. 2018;10(1):1-1. doi:10.1109/les.2018.2789942
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2018 | Journal Article | LibreCat-ID: 13057
Kampmann M, Hellebrand S. Design For Small Delay Test - A Simulation Study. Microelectronics Reliability. 2018;80:124-133.
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2017 | Journal Article | LibreCat-ID: 29462
Sadeghi-Kohan S, Kamal M, Navabi Z. Self-Adjusting Monitor for Measuring Aging Rate and Advancement. IEEE Transactions on Emerging Topics in Computing. 2017;8(3):627-641. doi:10.1109/tetc.2017.2771441
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2015 | Journal Article | LibreCat-ID: 13056
Huang Z, Liang H, Hellebrand S. A High Performance SEU Tolerant Latch. Journal of Electronic Testing - Theory and Applications (JETTA). 2015;31(4):349-359.
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2014 | Journal Article | LibreCat-ID: 13054
Hellebrand S, Wunderlich H-J. SAT-Based ATPG beyond Stuck-at Fault Testing. DeGruyter Journal on Information Technology (it). 2014;56(4):165-172.
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2014 | Journal Article | LibreCat-ID: 13055
Rodriguez Gomez L, Cook A, Indlekofer T, Hellebrand S, Wunderlich H-J. Adaptive Bayesian Diagnosis of Intermittent Faults. Journal of Electronic Testing - Theory and Applications (JETTA). 2014;30(5):527-540.
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2014 | Journal Article | LibreCat-ID: 46266
Alizadeh B, Behnam P, Sadeghi-Kohan S. A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. IEEE Transactions on Computers. Published online 2014:1-1. doi:10.1109/tc.2014.2329687
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2011 | Journal Article | LibreCat-ID: 13052
Hopsch F, Becker B, Hellebrand S, et al. Variation-Aware Fault Modeling. SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer. 2011;54(4):1813-1826.
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2007 | Journal Article | LibreCat-ID: 13036
Hellebrand S, G. Zoellin C, Wunderlich H-J, Ludwig S, Coym T, Straube B. Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. Informacije MIDEM, Ljubljana (Invited Paper). 2007;37(4 (124)):212-219.
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2007 | Journal Article | LibreCat-ID: 13044
Ali M, Hessler S, Welzl M, Hellebrand S. An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip. International Journal on High Performance Systems Architecture. 2007;1(2):113-123.
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2006 | Journal Article | LibreCat-ID: 13045
Becker B, Polian I, Hellebrand S, Straube B, Wunderlich H-J. DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme. it - Information Technology. 2006;48(5):305-311.
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2002 | Journal Article | LibreCat-ID: 13003
Hellebrand S, Wunderlich H-J, A. Ivaniuk A, V. Klimets Y, N. Yarmolik V. Efficient Online and Offline Testing of Embedded DRAMs. IEEE Transactions on Computers. 2002;51(7):801-809. doi:10.1109/tc.2002.1017700
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2002 | Journal Article | LibreCat-ID: 13069
Hellebrand S, Liang H-G, Wunderlich H-J. Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. Journal of Electronic Testing - Theory and Applications (JETTA). 2002;18(2):157-168.
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2002 | Journal Article | LibreCat-ID: 13070
Liang H, Hellebrand S, Wunderlich H-J. A Mixed-Mode BIST Scheme Based on Folding Compression. Journal on Computer Science and Technology. 2002;17(2):203-212.
LibreCat
2001 | Journal Article | LibreCat-ID: 13047
Liang H-G, Hellebrand S, Wunderlich H-J. Deterministic BIST Scheme Based on Reseeding of Folding Counters. Journal of Computer Research and Development, (Jisuanji Yanjiu yu Fazhan). 2001;38(8):931.
LibreCat
2001 | Journal Article | LibreCat-ID: 13068
Hellebrand S, Liang H-G, Wunderlich H-J. A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. Journal of Electronic Testing - Theory and Applications (JETTA). 2001;17(3/4):341-349.
LibreCat
1998 | Journal Article | LibreCat-ID: 13061
Hellebrand S, Wunderlich H-J, Hertwig A. Mixed-Mode BIST Using Embedded Processors. Journal of Electronic Testing Theory and Applications - JETTA. 1998;12(1/2):127-138.
LibreCat
1998 | Journal Article | LibreCat-ID: 13064
Hellebrand S, Hertwig A, Wunderlich H-J. Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. IEEE Design and Test. 1998;15(4):36-41.
LibreCat
1995 | Journal Article | LibreCat-ID: 13011
Hellebrand S, Rajski J, Tarnick S, Venkataraman S, Courtois B. Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Transactions on Computers. 1995;44(2):223-233. doi:10.1109/12.364534
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1992 | Journal Article | LibreCat-ID: 13017
Wunderlich H-J, Hellebrand S. The Pseudoexhaustive Test of Sequential Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). 1992;11(1):26-33. doi:10.1109/43.108616
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