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24 Publications
2023 | Journal Article | LibreCat-ID: 46264
Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2023). Workload-Aware Periodic Interconnect BIST. IEEE Design &Test, 1–1. https://doi.org/10.1109/mdat.2023.3298849
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2022 | Journal Article | LibreCat-ID: 29351
Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2022). Stress-Aware Periodic Test of Interconnects. Journal of Electronic Testing. https://doi.org/10.1007/s10836-021-05979-5
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2019 | Journal Article | LibreCat-ID: 8667
Sprenger, A., & Hellebrand, S. (2019). Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. Journal of Circuits, Systems and Computers, 28(1), 1–23. https://doi.org/10.1142/s0218126619400012
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2019 | Journal Article | LibreCat-ID: 13048
Kampmann, M., A. Kochte, M., Liu, C., Schneider, E., Hellebrand, S., & Wunderlich, H.-J. (2019). Built-in Test for Hidden Delay Faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 38(10), 1956–1968.
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2018 | Journal Article | LibreCat-ID: 12974
Hellebrand, S., Henkel, J., Raghunathan, A., & Wunderlich, H.-J. (2018). Guest Editors’ Introduction - Special Issue on Approximate Computing. IEEE Embedded Systems Letters, 10(1), 1–1. https://doi.org/10.1109/les.2018.2789942
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2018 | Journal Article | LibreCat-ID: 13057
Kampmann, M., & Hellebrand, S. (2018). Design For Small Delay Test - A Simulation Study. Microelectronics Reliability, 80, 124–133.
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2017 | Journal Article | LibreCat-ID: 29462
Sadeghi-Kohan, S., Kamal, M., & Navabi, Z. (2017). Self-Adjusting Monitor for Measuring Aging Rate and Advancement. IEEE Transactions on Emerging Topics in Computing, 8(3), 627–641. https://doi.org/10.1109/tetc.2017.2771441
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2015 | Journal Article | LibreCat-ID: 13056
Huang, Z., Liang, H., & Hellebrand, S. (2015). A High Performance SEU Tolerant Latch. Journal of Electronic Testing - Theory and Applications (JETTA), 31(4), 349–359.
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2014 | Journal Article | LibreCat-ID: 13054
Hellebrand, S., & Wunderlich, H.-J. (2014). SAT-Based ATPG beyond Stuck-at Fault Testing. DeGruyter Journal on Information Technology (It), 56(4), 165–172.
LibreCat
2014 | Journal Article | LibreCat-ID: 13055
Rodriguez Gomez, L., Cook, A., Indlekofer, T., Hellebrand, S., & Wunderlich, H.-J. (2014). Adaptive Bayesian Diagnosis of Intermittent Faults. Journal of Electronic Testing - Theory and Applications (JETTA), 30(5), 527–540.
LibreCat
2014 | Journal Article | LibreCat-ID: 46266
Alizadeh, B., Behnam, P., & Sadeghi-Kohan, S. (2014). A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. IEEE Transactions on Computers, 1–1. https://doi.org/10.1109/tc.2014.2329687
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2011 | Journal Article | LibreCat-ID: 13052
Hopsch, F., Becker, B., Hellebrand, S., Polian, I., Straube, B., Vermeiren, W., & Wunderlich, H.-J. (2011). Variation-Aware Fault Modeling. SCIENCE CHINA Information Sciences, Science China Press, Co-Published with Springer, 54(4), 1813–1826.
LibreCat
2007 | Journal Article | LibreCat-ID: 13036
Hellebrand, S., G. Zoellin, C., Wunderlich, H.-J., Ludwig, S., Coym, T., & Straube, B. (2007). Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance. Informacije MIDEM, Ljubljana (Invited Paper), 37(4 (124)), 212–219.
LibreCat
2007 | Journal Article | LibreCat-ID: 13044
Ali, M., Hessler, S., Welzl, M., & Hellebrand, S. (2007). An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip. International Journal on High Performance Systems Architecture, 1(2), 113–123.
LibreCat
2006 | Journal Article | LibreCat-ID: 13045
Becker, B., Polian, I., Hellebrand, S., Straube, B., & Wunderlich, H.-J. (2006). DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme. It - Information Technology, 48(5), 305–311.
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2002 | Journal Article | LibreCat-ID: 13003
Hellebrand, S., Wunderlich, H.-J., A. Ivaniuk, A., V. Klimets, Y., & N. Yarmolik, V. (2002). Efficient Online and Offline Testing of Embedded DRAMs. IEEE Transactions on Computers, 51(7), 801–809. https://doi.org/10.1109/tc.2002.1017700
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2002 | Journal Article | LibreCat-ID: 13069
Hellebrand, S., Liang, H.-G., & Wunderlich, H.-J. (2002). Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. Journal of Electronic Testing - Theory and Applications (JETTA), 18(2), 157–168.
LibreCat
2002 | Journal Article | LibreCat-ID: 13070
Liang, H., Hellebrand, S., & Wunderlich, H.-J. (2002). A Mixed-Mode BIST Scheme Based on Folding Compression. Journal on Computer Science and Technology, 17(2), 203–212.
LibreCat
2001 | Journal Article | LibreCat-ID: 13047
Liang, H.-G., Hellebrand, S., & Wunderlich, H.-J. (2001). Deterministic BIST Scheme Based on Reseeding of Folding Counters. Journal of Computer Research and Development, (Jisuanji Yanjiu Yu Fazhan), 38(8), 931.
LibreCat
2001 | Journal Article | LibreCat-ID: 13068
Hellebrand, S., Liang, H.-G., & Wunderlich, H.-J. (2001). A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. Journal of Electronic Testing - Theory and Applications (JETTA), 17(3/4), 341–349.
LibreCat
1998 | Journal Article | LibreCat-ID: 13061
Hellebrand, S., Wunderlich, H.-J., & Hertwig, A. (1998). Mixed-Mode BIST Using Embedded Processors. Journal of Electronic Testing Theory and Applications - JETTA, 12(1/2), 127–138.
LibreCat
1998 | Journal Article | LibreCat-ID: 13064
Hellebrand, S., Hertwig, A., & Wunderlich, H.-J. (1998). Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. IEEE Design and Test, 15(4), 36–41.
LibreCat
1995 | Journal Article | LibreCat-ID: 13011
Hellebrand, S., Rajski, J., Tarnick, S., Venkataraman, S., & Courtois, B. (1995). Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Transactions on Computers, 44(2), 223–233. https://doi.org/10.1109/12.364534
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1992 | Journal Article | LibreCat-ID: 13017
Wunderlich, H.-J., & Hellebrand, S. (1992). The Pseudoexhaustive Test of Sequential Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 11(1), 26–33. https://doi.org/10.1109/43.108616
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