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151 Publications


2024 | Conference Paper | LibreCat-ID: 52744
Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations
H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: European Test Symposium, The Hague, Netherlands, May 20-24, 2024, IEEE, n.d., p. 6.
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2024 | Conference Paper | LibreCat-ID: 52742
Vmin Testing under Variations: Defect vs. Fault Coverage
H. Jafarzadeh, F. Klemme, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024, IEEE, n.d., p. 6.
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2024 | Conference Paper | LibreCat-ID: 52743
Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle
S. Hellebrand, S. Sadeghi-Kohan, H.-J. Wunderlich, in: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, n.d., p. 1.
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2024 | Conference Paper | LibreCat-ID: 52745
Robust Test of Small Delay Faults under PVT-Variations
H.-J. Wunderlich, H. Jafarzadeh, S. Hellebrand, in: International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, n.d., p. 1.
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2024 | Misc | LibreCat-ID: 50284
Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression
A. Stiballe, J.D. Reimer, S. Sadeghi-Kohan, S. Hellebrand, Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression, 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024, Darmstadt, Germany, 2024.
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2024 | Misc | LibreCat-ID: 51799
Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks
M. Ustimova, S. Sadeghi-Kohan, S. Hellebrand, Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks, 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”  (TuZ’24), Feb. 2024, Darmstadt, Germany, 2024.
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2023 | Misc | LibreCat-ID: 35204
On Cryptography Effects on Interconnect Reliability
A. Ghazal, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, On Cryptography Effects on Interconnect Reliability, 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, Erfurt, Germany, 2023.
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2023 | Conference Paper | LibreCat-ID: 41875
Approximate Computing: Balancing Performance, Power, Reliability, and Safety
A. Badran, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: 28th IEEE European Test Symposium (ETS’23), May 2023, Venice, Italy, 2023.
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2023 | Conference Paper | LibreCat-ID: 46739
Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication
S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, in: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2023.
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2023 | Conference Paper | LibreCat-ID: 46738
Optimizing the Streaming of Sensor Data with Approximate Communication
S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, in: IEEE Asian Test Symposium (ATS’23), October 2023, Beijing, China, 2023.
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2023 | Journal Article | LibreCat-ID: 46264
Workload-Aware Periodic Interconnect BIST
S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, IEEE Design &Test (2023) 1–1.
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2023 | Conference Paper | LibreCat-ID: 45830
Robust Pattern Generation for Small Delay Faults under Process Variations
H. Jafarzadeh, F. Klemme, J.D. Reimer, Z.P. Najafi Haghi, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023, IEEE, Anaheim, CA, USA, 2023.
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2022 | Journal Article | LibreCat-ID: 29351
Stress-Aware Periodic Test of Interconnects
S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing (2022).
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2022 | Misc | LibreCat-ID: 29890
EM-Aware Interconnect BIST
S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, EM-Aware Interconnect BIST, European Workshop on Silicon Lifecycle Management, March 18, 2022, Online, 2022.
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2020 | Conference Paper | LibreCat-ID: 19422
Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study
A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, Virtual Conference - Originally Frascati (Rome), Italy, 2020.
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2020 | Misc | LibreCat-ID: 15419
Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects
S. Sadeghi-Kohan, S. Hellebrand, Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects, 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, Ludwigsburg, 2020.
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2020 | Conference Paper | LibreCat-ID: 29200
Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects
S. Sadeghi-Kohan, S. Hellebrand, in: 38th IEEE VLSI Test Symposium (VTS), IEEE, Virtual Conference - Originally San Diego, CA, USA, 2020.
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2020 | Conference Paper | LibreCat-ID: 19421
Logic Fault Diagnosis of Hidden Delay Defects
S. Holst, M. Kampmann, A. Sprenger, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, X. Weng, in: IEEE International Test Conference (ITC’20), November 2020, Virtual Conference - Originally Washington, DC, USA, 2020.
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2019 | Misc | LibreCat-ID: 8112
A Hybrid Space Compactor for Varying X-Rates
M.U. Maaz, A. Sprenger, S. Hellebrand, A Hybrid Space Compactor for Varying X-Rates, 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), Prien am Chiemsee, 2019.
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2019 | Journal Article | LibreCat-ID: 8667
Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test
A. Sprenger, S. Hellebrand, Journal of Circuits, Systems and Computers 28 (2019) 1–23.
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2019 | Journal Article | LibreCat-ID: 13048
Built-in Test for Hidden Delay Faults
M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, H.-J. Wunderlich, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38 (2019) 1956–1968.
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2019 | Conference Paper | LibreCat-ID: 12918
A Hybrid Space Compactor for Adaptive X-Handling
M.U. Maaz, A. Sprenger, S. Hellebrand, in: 50th IEEE International Test Conference (ITC), IEEE, Washington, DC, USA, 2019, pp. 1–8.
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2018 | Misc | LibreCat-ID: 4576
Stochastische Kompaktierung für den Hochgeschwindigkeitstest
A. Sprenger, S. Hellebrand, Stochastische Kompaktierung für den Hochgeschwindigkeitstest, 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), Freiburg, Germany, 2018.
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2018 | Journal Article | LibreCat-ID: 12974
Guest Editors' Introduction - Special Issue on Approximate Computing
S. Hellebrand, J. Henkel, A. Raghunathan, H.-J. Wunderlich, IEEE Embedded Systems Letters 10 (2018) 1–1.
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2018 | Journal Article | LibreCat-ID: 13057
Design For Small Delay Test - A Simulation Study
M. Kampmann, S. Hellebrand, Microelectronics Reliability 80 (2018) 124–133.
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2018 | Conference Paper | LibreCat-ID: 4575
Tuning Stochastic Space Compaction to Faster-than-at-Speed Test
A. Sprenger, S. Hellebrand, in: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, Budapest, Hungary, 2018.
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2018 | Conference Paper | LibreCat-ID: 10575
Extending Aging Monitors for Early Life and Wear-Out Failure Prevention
C. Liu, E. Schneider, M. Kampmann, S. Hellebrand, H.-J. Wunderlich, in: 27th IEEE Asian Test Symposium (ATS’18), 2018.
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2017 | Conference Paper | LibreCat-ID: 12973
Special Session on Early Life Failures
J. Deshmukh, W. Kunz, H.-J. Wunderlich, S. Hellebrand, in: 35th IEEE VLSI Test Symposium (VTS’17), IEEE, Caesars Palace, Las Vegas, Nevada, USA, 2017.
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2017 | Misc | LibreCat-ID: 13078
X-tolerante Prüfzellengruppierung für den Test mit erhöhter Betriebsfrequenz
M. Kampmann, S. Hellebrand, X-Tolerante Prüfzellengruppierung Für Den Test Mit Erhöhter Betriebsfrequenz, 29. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’17), Lübeck, Germany, 2017.
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2017 | Conference Paper | LibreCat-ID: 10576
Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test
M. Kampmann, S. Hellebrand, in: 20th IEEE International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS’17), IEEE, 2017.
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2016 | Conference Paper | LibreCat-ID: 12975
X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test
M. Kampmann, S. Hellebrand, in: 25th IEEE Asian Test Symposium (ATS’16), IEEE, Hiroshima, Japan, 2016, pp. 1–6.
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2015 | Conference Paper | LibreCat-ID: 12976
Optimized Selection of Frequencies for Faster-Than-at-Speed Test
M. Kampmann, M. A. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand, H.-J. Wunderlich, in: 24th IEEE Asian Test Symposium (ATS’15), IEEE, Mumbai, India, 2015, pp. 109–114.
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2015 | Journal Article | LibreCat-ID: 13056
A High Performance SEU Tolerant Latch
Z. Huang, H. Liang, S. Hellebrand, Journal of Electronic Testing - Theory and Applications (JETTA) 31 (2015) 349–359.
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2015 | Misc | LibreCat-ID: 13077
Effiziente Auswahl von Testfrequenzen für den Test kleiner Verzögerungsfehler
S. Hellebrand, T. Indlekofer, M. Kampmann, M. Kochte, C. Liu, H.-J. Wunderlich, Effiziente Auswahl von Testfrequenzen Für Den Test Kleiner Verzögerungsfehler, 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany, 2015.
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2014 | Conference Paper | LibreCat-ID: 12977
FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects
S. Hellebrand, T. Indlekofer, M. Kampmann, M. A. Kochte, C. Liu, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’14), IEEE, Seattle, Washington, USA, 2014.
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2014 | Journal Article | LibreCat-ID: 13054
SAT-Based ATPG beyond Stuck-at Fault Testing
S. Hellebrand, H.-J. Wunderlich, DeGruyter Journal on Information Technology (It) 56 (2014) 165–172.
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2014 | Journal Article | LibreCat-ID: 13055
Adaptive Bayesian Diagnosis of Intermittent Faults
L. Rodriguez Gomez, A. Cook, T. Indlekofer, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing - Theory and Applications (JETTA) 30 (2014) 527–540.
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2013 | Conference Paper | LibreCat-ID: 12979
Analyzing and Quantifying Fault Tolerance Properties
S. Hellebrand, in: 14th IEEE Latin American Test Workshop - (LATW’13), IEEE, Cordoba, Argentina, 2013.
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2013 | Misc | LibreCat-ID: 13075
Adaptive Test and Diagnosis of Intermittent Faults
A. Cook, L. Rodriguez Gomez, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, Adaptive Test and Diagnosis of Intermittent Faults, 14th Latin American Test Workshop, Cordoba, Argentina, 2013.
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2012 | Conference Paper | LibreCat-ID: 12980
Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test
A. Cook, S. Hellebrand, M. E. Imhof, A. Mumtaz, H.-J. Wunderlich, in: 13th IEEE Latin American Test Workshop (LATW’12), IEEE, Quito, Ecuador, 2012, pp. 1–4.
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2012 | Conference Paper | LibreCat-ID: 12981
Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test
A. Cook, S. Hellebrand, H.-J. Wunderlich, in: 17th IEEE European Test Symposium (ETS’12), IEEE, Annecy, France, 2012, pp. 1–6.
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2012 | Misc | LibreCat-ID: 13074
Eingebaute Selbstdiagnose mit zufälligen und deterministischen Mustern
A. Cook, S. Hellebrand, H.-J. Wunderlich, Eingebaute Selbstdiagnose Mit Zufälligen Und Deterministischen Mustern, 24. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’12), Cottbus, Germany, 2012.
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2011 | Conference Paper | LibreCat-ID: 12982
Diagnostic Test of Robust Circuits
A. Cook, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, in: 20th IEEE Asian Test Symposium (ATS’11), IEEE, New Delhi, India, 2011, pp. 285–290.
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2011 | Conference Paper | LibreCat-ID: 12984
Towards Variation-Aware Test Methods
I. Polian, B. Becker, S. Hellebrand, H.-J. Wunderlich, P. Maxwell, in: 16th IEEE European Test Symposium Trondheim (ETS’11), IEEE, Trondheim, Norway, 2011.
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2011 | Conference Paper | LibreCat-ID: 13053
Robuster Selbsttest mit Diagnose
A. Cook, S. Hellebrand, T. Indlekofer, H.-J. Wunderlich, in: 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit Und Entwurf,” Hamburg, Germany, 2011, pp. 48–53.
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2011 | Journal Article | LibreCat-ID: 13052
Variation-Aware Fault Modeling
F. Hopsch, B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, SCIENCE CHINA Information Sciences, Science China Press, Co-Published with Springer 54 (2011) 1813–1826.
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2010 | Misc | LibreCat-ID: 10670
Testdatenkompression mit Hilfe der Netzwerkinfrastruktur
V. Fröse, R. Ibers, S. Hellebrand, Testdatenkompression Mit Hilfe Der Netzwerkinfrastruktur, 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany, 2010.
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2010 | Conference Paper | LibreCat-ID: 12987
Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits
B. Becker, S. Hellebrand, I. Polian, B. Straube, W. Vermeiren, H.-J. Wunderlich, in: 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10), IEEE, Chicago, IL, USA, 2010.
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2010 | Conference Paper | LibreCat-ID: 13051
Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz
M. Hunger, S. Hellebrand, in: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf,” Wildbad Kreuth, Germany, 2010, pp. 81–88.
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2010 | Misc | LibreCat-ID: 13073
Nano-Electronic Systems
S. Hellebrand, Nano-Electronic Systems, Editorial, it 4/2010, pp. 179-180, 2010.
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