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165 Publications
1998 | Misc | LibreCat-ID: 13091
V. N. Yarmolik, S. Hellebrand, and H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories. 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1998.
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1998 | Misc | LibreCat-ID: 13092
V. N. Yarmolik, S. Hellebrand, and H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories. 10th GI/ITG/GMM/IEEE Workshop, 1998.
LibreCat
1998 | Book Chapter | LibreCat-ID: 13060
S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, “Mixed-Mode BIST Using Embedded Processors,” in Mixed-Mode BIST Using Embedded Processors, In: M. Nicolaidis, Y. Zorian, D. K. Pradhan (Eds.): On-Line Testing for VLSI, Boston: Kluwer Academic Publishers 1998: Kluwer Academic Publishers, 1998.
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1998 | Journal Article | LibreCat-ID: 13061
S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, “Mixed-Mode BIST Using Embedded Processors,” Journal of Electronic Testing Theory and Applications - JETTA, vol. 12, no. 1/2, pp. 127–138, 1998.
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1998 | Journal Article | LibreCat-ID: 13064
S. Hellebrand, A. Hertwig, and H.-J. Wunderlich, “Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications,” IEEE Design and Test, vol. 15, no. 4, pp. 36–41, 1998.
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1998 | Conference Paper | LibreCat-ID: 13007
A. Hertwig, S. Hellebrand, and H.-J. Wunderlich, “Fast Self-Recovering Controllers,” in 16th IEEE VLSI Test Symposium (VTS’98), 1998, pp. 296–302, doi: 10.1109/vtest.1998.670883.
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1998 | Conference Paper | LibreCat-ID: 13008
S. Hellebrand, H.-J. Wunderlich, and V. N. Yarmolik, “Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs,” in Design Automation and Test in Europe (DATE’98), 1998, pp. 173–179, doi: 10.1109/date.1998.655853.
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1998 | Conference Paper | LibreCat-ID: 13063
V. N. Yarmolik, Y. V. Klimets, S. Hellebrand, and H.-J. Wunderlich, “New Transparent RAM BIST Based on Self-Adjusting Output Data Compression,” in Design & Diagnostics of Electronic Circuits & Systems (DDECS’98), 1998, pp. 27–33.
LibreCat
1997 | Misc | LibreCat-ID: 13089
K.-H. Tsai, S. Hellebrand, J. Rajski, and M. Marek-Sadowska, STARBIST: Scan Autocorrelated Random Pattern Generation. 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1997.
LibreCat
1997 | Misc | LibreCat-ID: 13090
A. Hertwig, S. Hellebrand, and H.-J. Wunderlich, Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications. 3rd IEEE International On-Line Testing Workshop, Crete, Greece, 1997.
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1997 | Conference Paper | LibreCat-ID: 13009
K.-H. Tsai, S. Hellebrand, M. Marek-Sadowska, and J. Rajski, “STARBIST: Scan Autocorrelated Random Pattern Generation,” 1997, doi: 10.1109/dac.1997.597194.
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1996 | Misc | LibreCat-ID: 13087
S. Hellebrand and H.-J. Wunderlich, Using Embedded Processors for BIST. 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1996.
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1996 | Misc | LibreCat-ID: 13088
S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, Mixed-Mode BIST Using Embedded Processors. 2nd IEEE International On-Line Testing Workshop. Biarritz, France, 1996.
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1996 | Conference Paper | LibreCat-ID: 13010
S. Hellebrand, H.-J. Wunderlich, and A. Hertwig, “Mixed-Mode BIST Using Embedded Processors,” in IEEE International Test Conference (ITC’96), 1996, pp. 195–204, doi: 10.1109/test.1996.556962.
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1995 | Report | LibreCat-ID: 13026
S. Hellebrand and H.-J. Wunderlich, Synthesis Procedures for Self-Testable Controllers. University of Siegen, Germany, 1995.
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1995 | Report | LibreCat-ID: 13027
S. Hellebrand, H.-J. Wunderlich, F. Goncalves, and J. Paulo Teixeira, Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis. University Siegen, Germany, 1995.
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1995 | Report | LibreCat-ID: 13028
S. Hellebrand, M. Herzog, and H.-J. Wunderlich, Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing. University of Siegen, Germany, 1995.
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1995 | Misc | LibreCat-ID: 13086
S. Hellebrand, B. Reeb, S. Tarnick, and H.-J. Wunderlich, Pattern Generation for a Deterministic BIST Scheme. 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1995.
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1995 | Journal Article | LibreCat-ID: 13011
S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, “Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,” IEEE Transactions on Computers, vol. 44, no. 2, pp. 223–233, 1995, doi: 10.1109/12.364534.
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1995 | Conference Paper | LibreCat-ID: 13012
S. Hellebrand, B. Reeb, S. Tarnick, and H.-J. Wunderlich, “Pattern Generation for a Deterministic BIST Scheme,” in ACM/IEEE International Conference on Computer Aided Design (ICCAD’95), 1995, pp. 88–94, doi: 10.1109/iccad.1995.479997.
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1994 | Report | LibreCat-ID: 13024
S. Hellebrand, A. Juergensen, and H.-J. Wunderlich, Synthesis for Off-line Testability. University of Siegen, Germany, 1994.
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1994 | Report | LibreCat-ID: 13025
S. Hellebrand, A. Juergensen, A. Stroele, and H.-J. Wunderlich, Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time. University of Siegen, Germany, 1994.
LibreCat
1994 | Misc | LibreCat-ID: 13083
S. Venkataraman, J. Rajski, S. Hellebrand, and S. Tarnick, Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands, 1994.
LibreCat
1994 | Misc | LibreCat-ID: 13084
S. Hellebrand and H.-J. Wunderlich, Ein Verfahren zur testfreundlichen Steuerwerkssynthese. 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands, 1994.
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1994 | Misc | LibreCat-ID: 13085
S. Hellebrand, J. Paulo Teixeira, and H.-J. Wunderlich, Synthesis for Testability - the ARCHIMEDES Approach. 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1994.
LibreCat
1994 | Conference Paper | LibreCat-ID: 13014
S. Hellebrand and H.-J. Wunderlich, “An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures,” in ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94), 1994, pp. 110–116, doi: 10.1109/iccad.1994.629752.
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1994 | Conference Paper | LibreCat-ID: 13059
S. Hellebrand and H.-J. Wunderlich, “Synthese schneller selbsttestbarer Steuerwerke,” in Tagungsband der GI/GME/ITG-Fachtagung \& Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, 1994, pp. 3–11.
LibreCat
1994 | Conference Paper | LibreCat-ID: 13013
S. Hellebrand and H.-J. Wunderlich, “Synthesis of Self-Testable Controllers,” in European Design and Test Conference (EDAC/ETC/EUROASIC), 1994, pp. 580–585, doi: 10.1109/edtc.1994.326815.
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1993 | Misc | LibreCat-ID: 13081
S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, Effiziente Erzeugung deterministischer Muster im Selbsttest. 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany, 1993.
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1993 | Misc | LibreCat-ID: 13082
S. Hellebrand and H.-J. Wunderlich, Synthesis of Self-Testable Controllers. ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France, 1993.
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1993 | Conference Paper | LibreCat-ID: 13015
S. Venkataraman, J. Rajski, S. Hellebrand, and S. Tarnick, “An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers,” 1993, doi: 10.1109/iccad.1993.580117.
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1992 | Report | LibreCat-ID: 13023
S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. Institut National Polytechnique de Grenoble, Grenoble, France, 1992.
LibreCat
1992 | Misc | LibreCat-ID: 13076
S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. IEEE Design for Testability Workshop, Vail, CO, USA, 1992.
LibreCat
1992 | Misc | LibreCat-ID: 13080
S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs. Workshop on New Directions for Testing, Montreal, Canada, 1992.
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1992 | Journal Article | LibreCat-ID: 13017
H.-J. Wunderlich and S. Hellebrand, “The Pseudoexhaustive Test of Sequential Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 11, no. 1, pp. 26–33, 1992, doi: 10.1109/43.108616.
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1992 | Conference Paper | LibreCat-ID: 13016
S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, “Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers,” in IEEE International Test Conference (ITC’92), 1992, pp. 120–129, doi: 10.1109/test.1992.527812.
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1991 | Book | LibreCat-ID: 13034
S. Hellebrand, Synthese vollständig testbarer Schaltungen. Verlag Düsseldorf: VDI Verlag: Verlag Düsseldorf: VDI Verlag, 1991.
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1990 | Misc | LibreCat-ID: 13103
S. Hellebrand, H.-J. Wunderlich, and O. F. Haberl, Generating Pseudo-Exhaustive Vectors for External Testing. IEEE Design for Testability Workshop, Vail, CO, USA, 1990.
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1990 | Conference Paper | LibreCat-ID: 13018
S. Hellebrand and H.-J. Wunderlich, “Tools and Devices Supporting the Pseudo-Exhaustive Test,” in European Design Automation Conference (EDAC’90), 1990, pp. 13–17, doi: 10.1109/edac.1990.136612.
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1990 | Conference Paper | LibreCat-ID: 13019
S. Hellebrand, H.-J. Wunderlich, and O. F. Haberl, “Generating Pseudo-Exhaustive Vectors for External Testing,” in IEEE International Test Conference (ITC’90), 1990, pp. 670–679, doi: 10.1109/test.1990.114082.
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1989 | Conference Paper | LibreCat-ID: 13020
H.-J. Wunderlich and S. Hellebrand, “The Pseudo-Exhaustive Test of Sequential Circuits,” in IEEE International Test Conference (ITC’89), 1989, pp. 19–27, doi: 10.1109/test.1989.82273.
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1988 | Conference Paper | LibreCat-ID: 13021
H.-J. Wunderlich and S. Hellebrand, “Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits,” in 18th International Symposium on Fault-Tolerant Computing, FTCS-18, 1988, pp. 36–45, doi: 10.1109/ftcs.1988.5294.
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1988 | Conference Paper | LibreCat-ID: 13058
D. Schmid, H.-J. Wunderlich, F. Feldbusch, S. Hellebrand, J. Holzinger, and A. Kunzmann, “Integrated Tools for Automatic Design for Testability,” in Tool Integration and Design Environments, F.J. Rammig (Editor), 1988, pp. 233–258.
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1988 | Conference Paper | LibreCat-ID: 13062
S. Hellebrand and H.-J. Wunderlich, “Automatisierung des Entwurfs vollständig testbarer Schaltungen,” in GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188, 1988, pp. 145–159.
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1986 | Report | LibreCat-ID: 13022
S. Hellebrand, Deformation dicker Punkte und Netze von Quadriken. Universität Regensburg, Fakultät für Mathematik, Regensburg, Germany, 1986.
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