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136 Publications


2019 | Misc | LibreCat-ID: 8112
Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19); 2019.
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2019 | Journal Article | LibreCat-ID: 8667
Sprenger A, Hellebrand S. Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. Journal of Circuits, Systems and Computers. 2019;28(1):1-23. doi:10.1142/s0218126619400012
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2019 | Conference Paper | LibreCat-ID: 12918
Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Adaptive X-Handling. In: 50th IEEE International Test Conference (ITC). Washington, DC, USA: IEEE; 2019:1-8.
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2019 | Journal Article | LibreCat-ID: 13048
Kampmann M, A. Kochte M, Liu C, Schneider E, Hellebrand S, Wunderlich H-J. Built-in Test for Hidden Delay Faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). 2019;38(10):1956-1968.
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2018 | Misc | LibreCat-ID: 4576
Sprenger A, Hellebrand S. Stochastische Kompaktierung für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18); 2018.
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2018 | Journal Article | LibreCat-ID: 13057
Kampmann M, Hellebrand S. Design For Small Delay Test - A Simulation Study. Microelectronics Reliability. 2018;80:124-133.
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2018 | Misc | LibreCat-ID: 13072
Kampmann M, Hellebrand S. Optimized Constraints for Scan-Chain Insertion for Faster-than-at-Speed Test. 19th Workshop on RTL and High Level Testing (WRTLT’18), Hefei, Anhui, China; 2018.
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2018 | Journal Article | LibreCat-ID: 12974
Hellebrand S, Henkel J, Raghunathan A, Wunderlich H-J. Guest Editors’ Introduction - Special Issue on Approximate Computing. IEEE Embedded Systems Letters. 2018;10(1):1-1. doi:10.1109/les.2018.2789942
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2018 | Conference Paper | LibreCat-ID: 10575
Liu C, Schneider E, Kampmann M, Hellebrand S, Wunderlich H-J. Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. In: 2018 IEEE 27th Asian Test Symposium (ATS). ; 2018. doi:10.1109/ats.2018.00028
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2018 | Conference Paper | LibreCat-ID: 4575
Sprenger A, Hellebrand S. Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. In: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Budapest: IEEE; 2018. doi:10.1109/ddecs.2018.00020
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2017 | Conference Paper | LibreCat-ID: 10576
Kampmann M, Hellebrand S. Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. In: 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE; 2017. doi:10.1109/ddecs.2017.7934564
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2017 | Conference Paper | LibreCat-ID: 12973
Deshmukh J, Kunz W, Wunderlich H-J, Hellebrand S. Special Session on Early Life Failures. In: 35th IEEE VLSI Test Symposium (VTS’17). Caesars Palace, Las Vegas, Nevada, USA: IEEE; 2017. doi:10.1109/vts.2017.7928933
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2017 | Misc | LibreCat-ID: 13078
Kampmann M, Hellebrand S. X-Tolerante Prüfzellengruppierung Für Den Test Mit Erhöhter Betriebsfrequenz. 29. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’17), Lübeck, Germany; 2017.
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2016 | Conference Paper | LibreCat-ID: 12975
Kampmann M, Hellebrand S. X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test. In: 25th IEEE Asian Test Symposium (ATS’16). Hiroshima, Japan: IEEE; 2016:1-6. doi:10.1109/ats.2016.20
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2015 | Conference Paper | LibreCat-ID: 12976
Kampmann M, A. Kochte M, Schneider E, Indlekofer T, Hellebrand S, Wunderlich H-J. Optimized Selection of Frequencies for Faster-Than-at-Speed Test. In: 24th IEEE Asian Test Symposium (ATS’15). Mumbai, India: IEEE; 2015:109-114. doi:10.1109/ats.2015.26
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2015 | Journal Article | LibreCat-ID: 13056
Huang Z, Liang H, Hellebrand S. A High Performance SEU Tolerant Latch. Journal of Electronic Testing - Theory and Applications (JETTA). 2015;31(4):349-359.
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2015 | Misc | LibreCat-ID: 13077
Hellebrand S, Indlekofer T, Kampmann M, Kochte M, Liu C, Wunderlich H-J. Effiziente Auswahl von Testfrequenzen Für Den Test Kleiner Verzögerungsfehler. 27. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’15), Bad Urach, Germany; 2015.
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2014 | Conference Paper | LibreCat-ID: 12977
Hellebrand S, Indlekofer T, Kampmann M, A. Kochte M, Liu C, Wunderlich H-J. FAST-BIST: Faster-than-at-Speed BIST Targeting Hidden Delay Defects. In: IEEE International Test Conference (ITC’14). Seattle, Washington, USA: IEEE; 2014. doi:10.1109/test.2014.7035360
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2014 | Journal Article | LibreCat-ID: 13054
Hellebrand S, Wunderlich H-J. SAT-Based ATPG beyond Stuck-at Fault Testing. DeGruyter Journal on Information Technology (it). 2014;56(4):165-172.
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2014 | Journal Article | LibreCat-ID: 13055
Rodriguez Gomez L, Cook A, Indlekofer T, Hellebrand S, Wunderlich H-J. Adaptive Bayesian Diagnosis of Intermittent Faults. Journal of Electronic Testing - Theory and Applications (JETTA). 2014;30(5):527-540.
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2013 | Misc | LibreCat-ID: 13075
Cook A, Rodriguez Gomez L, Hellebrand S, Indlekofer T, Wunderlich H-J. Adaptive Test and Diagnosis of Intermittent Faults. 14th Latin American Test Workshop, Cordoba, Argentina; 2013.
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2013 | Conference Paper | LibreCat-ID: 12979
Hellebrand S. Analyzing and Quantifying Fault Tolerance Properties. In: 14th IEEE Latin American Test Workshop - (LATW’13). Cordoba, Argentina: IEEE; 2013. doi:10.1109/latw.2013.6562662
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2012 | Conference Paper | LibreCat-ID: 12980
Cook A, Hellebrand S, E. Imhof M, Mumtaz A, Wunderlich H-J. Built-in Self-Diagnosis Targeting Arbitrary Defects with Partial Pseudo-Exhaustive Test. In: 13th IEEE Latin American Test Workshop (LATW’12). Quito, Ecuador: IEEE; 2012:1-4. doi:10.1109/latw.2012.6261229
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2012 | Conference Paper | LibreCat-ID: 12981
Cook A, Hellebrand S, Wunderlich H-J. Built-in Self-Diagnosis Exploiting Strong Diagnostic Windows in Mixed-Mode Test. In: 17th IEEE European Test Symposium (ETS’12). Annecy, France: IEEE; 2012:1-6. doi:10.1109/ets.2012.6233025
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2012 | Misc | LibreCat-ID: 13074
Cook A, Hellebrand S, Wunderlich H-J. Eingebaute Selbstdiagnose Mit Zufälligen Und Deterministischen Mustern. 24. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’12), Cottbus, Germany; 2012.
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2011 | Conference Paper | LibreCat-ID: 12984
Polian I, Becker B, Hellebrand S, Wunderlich H-J, Maxwell P. Towards Variation-Aware Test Methods. In: 16th IEEE European Test Symposium Trondheim (ETS’11). Trondheim, Norway: IEEE; 2011. doi:10.1109/ets.2011.51
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2011 | Journal Article | LibreCat-ID: 13052
Hopsch F, Becker B, Hellebrand S, et al. Variation-Aware Fault Modeling. {SCIENCE CHINA Information Sciences, Science China Press, co-published with Springer}. 2011;54(4):1813-1826.
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2011 | Conference Paper | LibreCat-ID: 13053
Cook A, Hellebrand S, Indlekofer T, Wunderlich H-J. Robuster Selbsttest mit Diagnose. In: 5. GMM/GI/ITG Fachtagung “Zuverlässigkeit Und Entwurf.” Hamburg, Germany; 2011:48-53.
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2011 | Conference Paper | LibreCat-ID: 12982
Cook A, Hellebrand S, Indlekofer T, Wunderlich H-J. Diagnostic Test of Robust Circuits. In: 20th IEEE Asian Test Symposium (ATS’11). New Delhi, India: IEEE; 2011:285-290. doi:10.1109/ats.2011.55
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2010 | Conference Paper | LibreCat-ID: 12983
Hopsch F, Becker B, Hellebrand S, et al. Variation-Aware Fault Modeling. In: {19th IEEE Asian Test Symposium (ATS’10)}. Shanghai, China: {IEEE}; 2010:87-93. doi:10.1109/ats.2010.24
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2010 | Conference Paper | LibreCat-ID: 12988
Froese V, Ibers R, Hellebrand S. Reusing NoC-Infrastructure for Test Data Compression. In: {28th IEEE VLSI Test Symposium (VTS’10)}. Santa Cruz, CA, USA: {IEEE}; 2010:227-231. doi:10.1109/vts.2010.5469570
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2010 | Conference Paper | LibreCat-ID: 13049
Becker B, Hellebrand S, Polian I, Straube B, Vermeiren W, Wunderlich H-J. Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In: {4th Workshop on Dependable and Secure Nanocomputing (WDSN’10), (Invited Paper)}. Chicago, IL, USA; 2010.
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2010 | Conference Paper | LibreCat-ID: 13051
Hunger M, Hellebrand S. Ausbeute und Fehlertoleranz bei dreifach modularer Redundanz. In: 4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf.” Wildbad Kreuth, Germany; 2010:81-88.
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2010 | Conference Paper | LibreCat-ID: 12985
Indlekofer T, Schnittger M, Hellebrand S. Efficient Test Response Compaction for Robust BIST Using Parity Sequences. In: {28th IEEE International Conference on Computer Design (ICCD’10)}. Amsterdam, The Netherlands: {IEEE}; 2010:480-485. doi:10.1109/iccd.2010.5647648
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2010 | Misc | LibreCat-ID: 10670
Fröse V, Ibers R, Hellebrand S. Testdatenkompression Mit Hilfe Der Netzwerkinfrastruktur. 22. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’10), Paderborn, Germany; 2010.
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2010 | Conference Paper | LibreCat-ID: 12986
Hunger M, Hellebrand S. The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems. In: {25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’10)}. Kyoto, Japan: {IEEE}; 2010:101-108. doi:10.1109/dft.2010.19
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2010 | Misc | LibreCat-ID: 13073
Hellebrand S. Nano-Electronic Systems. Editorial, it 4/2010, pp. 179-180; 2010.
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2010 | Conference Paper | LibreCat-ID: 12987
Becker B, Hellebrand S, Polian I, Straube B, Vermeiren W, Wunderlich H-J. Massive Statistical Process Variations - A Grand Challenge for Testing Nanoelectronic Circuits. In: 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W’10). Chicago, IL, USA: IEEE; 2010. doi:10.1109/dsnw.2010.5542612
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2010 | Conference Paper | LibreCat-ID: 13050
Indlekofer T, Schnittger M, Hellebrand S. Robuster Selbsttest mit extremer Kompaktierung. In: {4. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf”}. Wildbad Kreuth, Germany; 2010:17-24.
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2009 | Conference Paper | LibreCat-ID: 12990
Hellebrand S, Hunger M. Are Robust Circuits Really Robust? In: {24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’09), (Invited Talk)}. Chicago, IL, USA: {IEEE}; 2009:77. doi:10.1109/dft.2009.28
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2009 | Conference Paper | LibreCat-ID: 12991
Hunger M, Hellebrand S, Czutro A, Polian I, Becker B. ATPG-Based Grading of Strong Fault-Secureness. In: {15th IEEE International On-Line Testing Symposium (IOLTS’09)}. Sesimbra-Lisbon, Portugal: {IEEE}; 2009. doi:10.1109/iolts.2009.5196027
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2009 | Conference Paper | LibreCat-ID: 13030
Hunger M, Hellebrand S, Czutro A, Polian I, Becker B. Robustheitsanalyse stark fehlersicherer Schaltungen mit SAT-basierter Testmustererzeugung. In: {3. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf”}. Stuttgart, Germany; 2009.
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2008 | Conference Paper | LibreCat-ID: 13032
Oehler P, Bosio A, Di Natale G, Hellebrand S. Modularer Selbsttest und optimierte Reparaturanalyse. In: {2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf”}. Ingolstadt, Germany; 2008.
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2008 | Misc | LibreCat-ID: 13033
Coym T, Hellebrand S, Ludwig S, Straube B, Wunderlich H-J, G. Zoellin C. Ein Verfeinertes Elektrisches Modell Für Teilchentreffer Und Dessen Auswirkung Auf Die Bewertung Der Schaltungsempfindlichkeit. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (Poster), Wien, Österreich; 2008.
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2008 | Conference Paper | LibreCat-ID: 12992
Oehler P, Bosio A, di Natale G, Hellebrand S. A Modular Memory BIST for Optimized Memory Repair. In: {14th IEEE International On-Line Testing Symposium (IOLTS’08), (Poster)}. Rhodos, Greece: {IEEE}; 2008. doi:10.1109/iolts.2008.30
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2008 | Conference Paper | LibreCat-ID: 12993
Hunger M, Hellebrand S. Verification and Analysis of Self-Checking Properties through ATPG. In: {14th IEEE International On-Line Testing Symposium (IOLTS’08)}. Rhodos, Greece: {IEEE}; 2008. doi:10.1109/iolts.2008.32
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2008 | Misc | LibreCat-ID: 13035
Amgalan U, Hachmann C, Hellebrand S, Wunderlich H-J. Testen Mit Rücksetzpunkten - Ein Ansatz Zur Verbesserung Der Ausbeute Bei Robusten Schaltungen. 20. ITG/GI/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Wien, Österreich; 2008.
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2008 | Conference Paper | LibreCat-ID: 12994
Amgalan U, Hachmann C, Hellebrand S, Wunderlich H-J. Signature Rollback - A Technique for Testing Robust Circuits. In: {26th IEEE VLSI Test Symposium (VTS’08)}. San Diego, CA, USA: {IEEE}; 2008:125-130. doi:10.1109/vts.2008.34
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2008 | Conference Paper | LibreCat-ID: 13031
Hunger M, Hellebrand S. Analyse selbstprüfender Schaltungen – Nachweis von Fehlersicherheit und Selbsttestbarkeit mit ATPG. In: {2. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf”}. Ingolstadt, Germany; 2008.
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2007 | Conference Paper | LibreCat-ID: 12995
Hellebrand S, G. Zoellin C, Wunderlich H-J, Ludwig S, Coym T, Straube B. A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. In: {22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT’07)}. Rome, Italy: {IEEE}; 2007:50-58. doi:10.1109/dft.2007.43
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