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136 Publications


1997 | Misc | LibreCat-ID: 13089
STARBIST: Scan Autocorrelated Random Pattern Generation
K.-H. Tsai, S. Hellebrand, J. Rajski, M. Marek-Sadowska, STARBIST: Scan Autocorrelated Random Pattern Generation, 4th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1997.
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1997 | Conference Paper | LibreCat-ID: 13009
STARBIST: Scan Autocorrelated Random Pattern Generation
K.-H. Tsai, S. Hellebrand, M. Marek-Sadowska, J. Rajski, in: {34th ACM/IEEE Design Automation Conference (DAC’97)}, {IEEE}, Anaheim, CA, USA, 1997.
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1996 | Misc | LibreCat-ID: 13087
Using Embedded Processors for BIST
S. Hellebrand, H.-J. Wunderlich, Using Embedded Processors for BIST, 3rd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1996.
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1996 | Misc | LibreCat-ID: 13088
Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, Mixed-Mode BIST Using Embedded Processors, 2nd IEEE International On-Line Testing Workshop. Biarritz, France, 1996.
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1996 | Conference Paper | LibreCat-ID: 13010
Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, in: {IEEE International Test Conference (ITC’96)}, {IEEE}, Washington, DC, USA, 1996, pp. 195–204.
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1995 | Report | LibreCat-ID: 13026
Synthesis Procedures for Self-Testable Controllers
S. Hellebrand, H.-J. Wunderlich, Synthesis Procedures for Self-Testable Controllers, University of Siegen, Germany, 1995.
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1995 | Report | LibreCat-ID: 13027
Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis
S. Hellebrand, H.-J. Wunderlich, F. Goncalves, J. Paulo Teixeira, Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis, University Siegen, Germany, 1995.
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1995 | Journal Article | LibreCat-ID: 13011
Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois, {IEEE Transactions on Computers} 44 (1995) 223–233.
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1995 | Report | LibreCat-ID: 13028
Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing
S. Hellebrand, M. Herzog, H.-J. Wunderlich, Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing, University of Siegen, Germany, 1995.
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1995 | Conference Paper | LibreCat-ID: 13012
Pattern Generation for a Deterministic BIST Scheme
S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich, in: {ACM/IEEE International Conference on Computer Aided Design (ICCAD’95)}, {IEEE (Comput. Soc. Press)}, San Jose, CA, USA, 1995, pp. 88–94.
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1995 | Misc | LibreCat-ID: 13086
Pattern Generation for a Deterministic BIST Scheme
S. Hellebrand, B. Reeb, S. Tarnick, H.-J. Wunderlich, Pattern Generation for a Deterministic BIST Scheme, 2nd IEEE International Test Synthesis Workshop, Santa Barbara, CA, 1995.
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1994 | Conference Paper | LibreCat-ID: 13013
Synthesis of Self-Testable Controllers
S. Hellebrand, H.-J. Wunderlich, in: {European Design and Test Conference (EDAC/ETC/EUROASIC)}, {IEEE (Comput. Soc. Press)}, Paris, France, 1994, pp. 580–585.
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1994 | Report | LibreCat-ID: 13025
Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time
S. Hellebrand, A. Juergensen, A. Stroele, H.-J. Wunderlich, Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time, University of Siegen, Germany, 1994.
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1994 | Conference Paper | LibreCat-ID: 13014
An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures
S. Hellebrand, H.-J. Wunderlich, in: {ACM/IEEE International Conference on Computer-Aided Design (ICCAD’94)}, {IEEE}, San Jose, CA, USA, 1994, pp. 110–116.
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1994 | Misc | LibreCat-ID: 13083
Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen
S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick, Effiziente Testsatzkodierung Für Prüfpfad-Basierte Selbsttestarchitekturen, 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands, 1994.
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1994 | Misc | LibreCat-ID: 13084
Ein Verfahren zur testfreundlichen Steuerwerkssynthese
S. Hellebrand, H.-J. Wunderlich, Ein Verfahren Zur Testfreundlichen Steuerwerkssynthese, 6th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Vaals, The Netherlands, 1994.
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1994 | Conference Paper | LibreCat-ID: 13059
Synthese schneller selbsttestbarer Steuerwerke
S. Hellebrand, H.-J. Wunderlich, in: {Tagungsband Der GI/GME/ITG-Fachtagung \& Rechnergestützter Entwurf Und Architektur Mikroelektronischer Systeme}, Oberwiesenthal, Informatik Xpress 4, TU Chemnitz Zwickau, Germany, 1994, pp. 3–11.
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1994 | Misc | LibreCat-ID: 13085
Synthesis for Testability - the ARCHIMEDES Approach
S. Hellebrand, J. Paulo Teixeira, H.-J. Wunderlich, Synthesis for Testability - the ARCHIMEDES Approach, 1st IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1994.
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1994 | Report | LibreCat-ID: 13024
Synthesis for Off-line Testability
S. Hellebrand, A. Juergensen, H.-J. Wunderlich, Synthesis for Off-Line Testability, University of Siegen, Germany, 1994.
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1993 | Misc | LibreCat-ID: 13082
Synthesis of Self-Testable Controllers
S. Hellebrand, H.-J. Wunderlich, Synthesis of Self-Testable Controllers, ARCHIMEDES Open Workshop on “Synthesis - Architectural Testability Support”, Montpellier, France, 1993.
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1993 | Conference Paper | LibreCat-ID: 13015
An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers
S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick, in: {ACM/IEEE International Conference on Computer Aided Design (ICCAD’93)}, {IEEE (Comput. Soc. Press)}, 1993.
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1993 | Misc | LibreCat-ID: 13081
Effiziente Erzeugung deterministischer Muster im Selbsttest
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, Effiziente Erzeugung Deterministischer Muster Im Selbsttest, 5th ITG/GI/GME Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Holzhau, Germany, 1993.
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1992 | Misc | LibreCat-ID: 13076
Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs, IEEE Design for Testability Workshop, Vail, CO, USA, 1992.
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1992 | Conference Paper | LibreCat-ID: 13016
Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, in: {IEEE International Test Conference (ITC’92)}, {IEEE}, Baltimore, MD, USA, 1992, pp. 120–129.
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1992 | Report | LibreCat-ID: 13023
Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs, Institut National Polytechnique de Grenoble, Grenoble, France, 1992.
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1992 | Misc | LibreCat-ID: 13080
Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs
S. Hellebrand, S. Tarnick, J. Rajski, B. Courtois, Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs, Workshop on New Directions for Testing, Montreal, Canada, 1992.
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1992 | Journal Article | LibreCat-ID: 13017
The Pseudoexhaustive Test of Sequential Circuits
H.-J. Wunderlich, S. Hellebrand, {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)} 11 (1992) 26–33.
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1991 | Book | LibreCat-ID: 13034
Synthese vollständig testbarer Schaltungen
S. Hellebrand, Synthese Vollständig Testbarer Schaltungen, Verlag Düsseldorf: VDI Verlag, Verlag Düsseldorf: VDI Verlag, 1991.
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1990 | Conference Paper | LibreCat-ID: 13018
Tools and Devices Supporting the Pseudo-Exhaustive Test
S. Hellebrand, H.-J. Wunderlich, in: {European Design Automation Conference (EDAC’90)}, {IEEE (Comput. Soc. Press)}, Glasgow, UK, 1990, pp. 13–17.
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1990 | Conference Paper | LibreCat-ID: 13019
Generating Pseudo-Exhaustive Vectors for External Testing
S. Hellebrand, H.-J. Wunderlich, O. F. Haberl, in: {IEEE International Test Conference (ITC’90)}, {IEEE (Comput. Soc. Press)}, Washington, DC, USA, 1990, pp. 670–679.
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1990 | Misc | LibreCat-ID: 13103
Generating Pseudo-Exhaustive Vectors for External Testing
S. Hellebrand, H.-J. Wunderlich, O. F. Haberl, Generating Pseudo-Exhaustive Vectors for External Testing, IEEE Design for Testability Workshop, Vail, CO, USA, 1990.
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1989 | Conference Paper | LibreCat-ID: 13020
The Pseudo-Exhaustive Test of Sequential Circuits
H.-J. Wunderlich, S. Hellebrand, in: {IEEE International Test Conference (ITC’89)}, {IEEE (Comput. Soc. Press)}, Washington, DC, USA, 1989, pp. 19–27.
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1988 | Conference Paper | LibreCat-ID: 13021
Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits
H.-J. Wunderlich, S. Hellebrand, in: {18th International Symposium on Fault-Tolerant Computing, FTCS-18}, {IEEE (Comput. Soc. Press)}, Tokyo, Japan, 1988, pp. 36–45.
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1988 | Conference Paper | LibreCat-ID: 13058
Integrated Tools for Automatic Design for Testability
D. Schmid, H.-J. Wunderlich, F. Feldbusch, S. Hellebrand, J. Holzinger, A. Kunzmann, in: {In: Tool Integration and Design Environments, F.J. Rammig (Editor)}, Amsterdam: Elsevier Science Publishers B.V.(North Holland), IFIP, Amsterdam, The Netherlands, 1988, pp. 233–258.
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1988 | Conference Paper | LibreCat-ID: 13062
Automatisierung des Entwurfs vollständig testbarer Schaltungen
S. Hellebrand, H.-J. Wunderlich, in: {GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188}, Springer Verlag, Hamburg, Germany, 1988, pp. 145–159.
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1986 | Report | LibreCat-ID: 13022
Deformation dicker Punkte und Netze von Quadriken
S. Hellebrand, Deformation Dicker Punkte Und Netze von Quadriken, Universität Regensburg, Fakultät für Mathematik, Regensburg, Germany, 1986.
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