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136 Publications


2007 | Conference Paper | LibreCat-ID: 13037
Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, in: {43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM’07), (Invited Paper)}, Bled, Slovenia, 2007.
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2007 | Journal Article | LibreCat-ID: 13044
An Efficient Fault Tolerant Mechanism to Deal with Permanent and Transient Failures in a Network on Chip
M. Ali, S. Hessler, M. Welzl, S. Hellebrand, {International Journal on High Performance Systems Architecture} 1 (2007) 113–123.
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2007 | Conference Paper | LibreCat-ID: 12996
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: {10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)}, {IEEE}, Krakow, Poland, 2007, pp. 185–190.
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2007 | Misc | LibreCat-ID: 13038
Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing
S. Hellebrand, Reliable Nanoscale Systems - Challenges and Strategies for On- and Offline Testing, 5th IEEE East-West Design \& Test Symposium, Yerevan, Armenia (Invited Talk), 2007.
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2007 | Conference Paper | LibreCat-ID: 13040
A Fault Tolerant Mechanism for Handling Permanent and Transient Failures in a Network on Chip
M. Ali, M. Welzl, S. Hessler, S. Hellebrand, in: {4th International Conference on Information Technology: New Generations (ITNG’07)}, Las Vegas, Nevada, USA, 2007, pp. 1027–1032.
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2007 | Misc | LibreCat-ID: 13039
An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips
M. Ali, M. Welzl, S. Hessler, S. Hellebrand, An End-to-End Reliability Protocol to Address Transient Faults in Network on Chips, DATE 2007 Friday Workshop on Diagnostic Services in Network-on-Chips, Nice, France, (Poster), 2007.
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2007 | Conference Paper | LibreCat-ID: 13041
Test und Zuverlässigkeit nanoelektronischer Systeme
B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich, in: {1. GMM/GI/ITG-Fachtagung “Zuverlässigkeit Und Entwurf”}, Munich, Germany, 2007.
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2007 | Conference Paper | LibreCat-ID: 12997
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy
P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: {12th IEEE European Test Symposium (ETS’07)}, {IEEE}, Freiburg, Germany, 2007, pp. 91–96.
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2007 | Misc | LibreCat-ID: 13042
An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy
P. Oehler, S. Hellebrand, H.-J. Wunderlich, An Integrated Built-in Test and Repair Approach for Memories with 2D Redundancy, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Erlangen, Germany, 2007.
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2007 | Journal Article | LibreCat-ID: 13036
Testing and Monitoring Nanoscale Systems - Challenges and Strategies for Advanced Quality Assurance
S. Hellebrand, C. G. Zoellin, H.-J. Wunderlich, S. Ludwig, T. Coym, B. Straube, {Informacije MIDEM, Ljubljana (Invited Paper)} 37 (2007) 212–219.
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2007 | Misc | LibreCat-ID: 13043
Qualitätssicherung für Nanochips - Wie IT-Produkte zuverlässig werden
S. Hellebrand, Qualitätssicherung Für Nanochips - Wie IT-Produkte Zuverlässig Werden, ForschungsForum Paderborn, 10. Ausgabe, Paderborn, Germany, 2007.
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2006 | Journal Article | LibreCat-ID: 13045
DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme
B. Becker, I. Polian, S. Hellebrand, B. Straube, H.-J. Wunderlich, {it -Information Technology} 48 (2006) 305–311.
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2005 | Misc | LibreCat-ID: 13102
Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study
P. Oehler, S. Hellebrand, Power Consumption Versus Error Correcting Capabilities in Embedded DRAMs - A Case Study, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
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2005 | Misc | LibreCat-ID: 13046
A Low Power Design for Embedded DRAMs with Online Consistency Checking
P. Oehler, S. Hellebrand, A Low Power Design for Embedded DRAMs with Online Consistency Checking, Kleinheubachertagung 2005, Miltenberg, Germany, 2005.
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2005 | Conference Paper | LibreCat-ID: 12998
A Dynamic Routing Mechanism for Network on Chip
M. Ali, M. Welzl, S. Hellebrand, in: {23rd IEEE NORCHIP Conference}, {IEEE}, Oulu, Finland, 2005, pp. 70–73.
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2005 | Conference Paper | LibreCat-ID: 12999
Considerations for Fault-Tolerant Networks on Chips
M. Ali, M. Welzl, M. Zwicknagl, S. Hellebrand, in: {IEEE International Conference on Microelectronics (ICM’05)}, {IEEE}, Islamabad, Pakistan, 2005.
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2005 | Conference Paper | LibreCat-ID: 13000
Low Power Embedded DRAMs with High Quality Error Correcting Capabilities
P. Oehler, S. Hellebrand, in: {10th IEEE European Test Symposium (ETS’05)}, {IEEE}, Tallinn, Estonia, 2005, pp. 148–153.
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2005 | Misc | LibreCat-ID: 13101
Dynamic Routing: A Prerequisite for Reliable NoCs
M. Ali, M. Welzl, S. Hellebrand, Dynamic Routing: A Prerequisite for Reliable NoCs, 17th GI/ITG/GMM Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”, Innsbruck, Austria, 2005.
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2004 | Conference Paper | LibreCat-ID: 13001
Data Compression for Multiple Scan Chains Using Dictionaries with Corrections
A. Wuertenberger, C. S. Tautermann, S. Hellebrand, in: {IEEE International Test Conference (ITC’04)}, {IEEE}, Charlotte, NC, USA, 2004, pp. 926–935.
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2004 | Misc | LibreCat-ID: 13099
Im Westen viel Neues - Informatik an der Universität Innsbruck
R. Breu, T. Fahringer, D. Fensel, S. Hellebrand, A. Middeldorp, O. Scherzer, Im Westen Viel Neues - Informatik an Der Universität Innsbruck, OCG Journal, pp. 28-29, 2004.
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2004 | Conference Paper | LibreCat-ID: 13071
Sensor Networks with More Features Using Less Hardware
M. Liu Jing, S. Ruehrup, C. Schindelhauer, K. Volbert, M. Dierkes, A. Bellgardt, R. Ibers, U. Hilleringmann, in: {GOR/NGB Conference Tilburg 2004}, Tilburg, Netherlands, 2004.
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2004 | Misc | LibreCat-ID: 13100
Data Compression for Multiple Scan Chains Using Dictionaries with Corrections
S. Hellebrand, A. Wuertenberger, C. S. Tautermann, Data Compression for Multiple Scan Chains Using Dictionaries with Corrections, 9th IEEE European Test Symposium, Ajaccio, Corsica, France, 2004.
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2003 | Conference Paper | LibreCat-ID: 13002
A Hybrid Coding Strategy for Optimized Test Data Compression
A. Wuertenberger, C. S. Tautermann, S. Hellebrand, in: {IEEE International Test Conference (ITC’03)}, {IEEE}, Charlotte, NC, USA, 2003, pp. 451–459.
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2003 | Misc | LibreCat-ID: 13098
Experiences from Teaching Software Development in a Java Environment
R. Breu, S. Hellebrand, M. Welzl, Experiences from Teaching Software Development in a Java Environment, Handouts ACS/IEEE Workshop on Practice and Experience with Java in Education, Tunis, Tunisia, 2003.
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2002 | Journal Article | LibreCat-ID: 13070
A Mixed-Mode BIST Scheme Based on Folding Compression
H. Liang, S. Hellebrand, H.-J. Wunderlich, {Journal on Computer Science and Technology} 17 (2002) 203–212.
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2002 | Journal Article | LibreCat-ID: 13069
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, {Journal of Electronic Testing - Theory and Applications (JETTA)} 18 (2002) 157–168.
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2002 | Journal Article | LibreCat-ID: 13003
Efficient Online and Offline Testing of Embedded DRAMs
S. Hellebrand, H.-J. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, V. N. Yarmolik, {IEEE Transactions on Computers} 51 (2002) 801–809.
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2002 | Misc | LibreCat-ID: 13097
Alternating Run-Length Coding: A Technique for Improved Test Data Compression
S. Hellebrand, A. Wuertenberger, Alternating Run-Length Coding: A Technique for Improved Test Data Compression, IEEE International Workshop on Test Resource Partitioning, Baltimore, MD, USA, 2002.
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2001 | Journal Article | LibreCat-ID: 13068
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, {Journal of Electronic Testing - Theory and Applications (JETTA)} 17 (2001) 341–349.
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2001 | Misc | LibreCat-ID: 13096
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
H.-G. Liang, S. Hellebrand, H.-J. Wunderlich, Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST, IEEE European Test Workshop, Stockholm, Sweden, 2001.
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2001 | Conference Paper | LibreCat-ID: 13004
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
H.-G. Liang, S. Hellebrand, H.-J. Wunderlich, in: {IEEE International Test Conference (ITC’01)}, {IEEE}, Baltimore, MD, USA, 2001, pp. 894–902.
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2001 | Journal Article | LibreCat-ID: 13047
Deterministic BIST Scheme Based on Reseeding of Folding Counters
H.-G. Liang, S. Hellebrand, H.-J. Wunderlich, {Journal of Computer Research and Development, (Jisuanji Yanjiu Yu Fazhan)} 38 (2001) 931.
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2000 | Misc | LibreCat-ID: 13094
Hardwarepraktikum im Diplomstudiengang Informatik
S. Hellebrand, H.-J. Wunderlich, Hardwarepraktikum Im Diplomstudiengang Informatik, Handbuch Lehre, Berlin, Raabe Verlag, 2000.
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2000 | Misc | LibreCat-ID: 13095
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters, IEEE European Test Workshop, Cascais, Portugal, 2000.
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2000 | Conference Paper | LibreCat-ID: 13005
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
S. Hellebrand, H.-G. Liang, H.-J. Wunderlich, in: {IEEE International Test Conference (ITC’00)}, {IEEE}, Atlantic City, NJ, USA, 2000, pp. 778–784.
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1999 | Conference Paper | LibreCat-ID: 13006
Error Detecting Refreshment for Embedded DRAMs
S. Hellebrand, H.-J. Wunderlich, A. A. Ivaniuk, Y. V. Klimets, V. N. Yarmolik, in: {17th IEEE VLSI Test Symposium (VTS’99)}, {IEEE (Comput. Soc.)}, Dana Point, CA, USA, 1999, pp. 384–390.
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1999 | Book | LibreCat-ID: 13065
Selbsttestbare Steuerwerke - Strukturen und Syntheseverfahren
S. Hellebrand, Selbsttestbare Steuerwerke - Strukturen Und Syntheseverfahren, Verlag Dr. Kovac, Hamburg, Verlag Dr. Kovac, Hamburg, 1999.
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1999 | Conference Paper | LibreCat-ID: 13066
Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms
V. N. Yarmolik, I. V. Bykov, S. Hellebrand, H.-J. Wunderlich, in: {Third European Dependable Computing Conference (EDCC-3)}, Prague, Czech Republic, 1999.
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1999 | Conference Paper | LibreCat-ID: 13067
Symmetric Transparent BIST for RAMs
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, in: {Design, Automation and Test in Europe (DATE’99)}, Munich, Germany, 1999, pp. 702–707.
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1999 | Misc | LibreCat-ID: 13093
Exploiting Symmetries to Speed Up Transparent BIST
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, Exploiting Symmetries to Speed Up Transparent BIST, 11th GI/ITG/GMM/IEEE Workshop, 1999.
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1998 | Conference Paper | LibreCat-ID: 13063
New Transparent RAM BIST Based on Self-Adjusting Output Data Compression
V. N. Yarmolik, Y. V. Klimets, S. Hellebrand, H.-J. Wunderlich, in: {Design \& Diagnostics of Electronic Circuits \& Systems}, Szczyrk, Poland, 1998, pp. 27–33.
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1998 | Conference Paper | LibreCat-ID: 13007
Fast Self-Recovering Controllers
A. Hertwig, S. Hellebrand, H.-J. Wunderlich, in: {16th IEEE VLSI Test Symposium (VTS’98)}, {IEEE (Comput. Soc.)}, Monterey, CA, USA, 1998, pp. 296–302.
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1998 | Journal Article | LibreCat-ID: 13064
Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications
S. Hellebrand, A. Hertwig, H.-J. Wunderlich, {IEEE Design and Test} 15 (1998) 36–41.
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1998 | Book Chapter | LibreCat-ID: 13060
Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, in: Mixed-Mode BIST Using Embedded Processors, {Kluwer Academic Publishers}, In: M. Nicolaidis, Y. Zorian, D. K. Pradhan (Eds.): On-Line Testing for VLSI, Boston: Kluwer Academic Publishers 1998, 1998.
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1998 | Misc | LibreCat-ID: 13091
Efficient Consistency Checking for Embedded Memories
V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories, 5th IEEE International Test Synthesis Workshop, Santa Barbara, CA, USA, 1998.
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1998 | Conference Paper | LibreCat-ID: 13008
Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs
S. Hellebrand, H.-J. Wunderlich, V. N. Yarmolik, in: {IEEE Design, Automation and Test in Europe (DATE’98)}, {IEEE (Comput.Soc)}, Paris, France, 1998, pp. 173–179.
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1998 | Journal Article | LibreCat-ID: 13061
Mixed-Mode BIST Using Embedded Processors
S. Hellebrand, H.-J. Wunderlich, A. Hertwig, {Journal of Electronic Testing Theory and Applications - JETTA} 12 (1998) 127–138.
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1998 | Misc | LibreCat-ID: 13092
Efficient Consistency Checking for Embedded Memories
V. N. Yarmolik, S. Hellebrand, H.-J. Wunderlich, Efficient Consistency Checking for Embedded Memories, 10th GI/ITG/GMM/IEEE Workshop, 1998.
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1998 | Report | LibreCat-ID: 13029
Test und Synthese schneller eingebetteter Systeme
S. Hellebrand, H.-J. Wunderlich, Test Und Synthese Schneller Eingebetteter Systeme, Universität Stuttgart, 1998.
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1997 | Misc | LibreCat-ID: 13090
Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications
A. Hertwig, S. Hellebrand, H.-J. Wunderlich, Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications, 3rd IEEE International On-Line Testing Workshop, Crete, Greece, 1997.
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